476 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_detect_pch()  local
483 		dev_priv->pch_type = PCH_NOP;  in intel_detect_pch()
501 			dev_priv->pch_id = id;  in intel_detect_pch()
504 				dev_priv->pch_type = PCH_IBX;  in intel_detect_pch()
508 				dev_priv->pch_type = PCH_CPT;  in intel_detect_pch()
513 				dev_priv->pch_type = PCH_CPT;  in intel_detect_pch()
517 				dev_priv->pch_type = PCH_LPT;  in intel_detect_pch()
522 				dev_priv->pch_type = PCH_LPT;  in intel_detect_pch()
527 				dev_priv->pch_type = PCH_SPT;  in intel_detect_pch()
531 				dev_priv->pch_type = PCH_SPT;  in intel_detect_pch()
538 				dev_priv->pch_type = intel_virt_detect_pch(dev);  in intel_detect_pch()
596 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)  in intel_suspend_encoders()  argument
598 	struct drm_device *dev = dev_priv->dev;  in intel_suspend_encoders()
611 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
612 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
614 static int skl_resume_prepare(struct drm_i915_private *dev_priv);
615 static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
620 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_drm_suspend()  local
625 	mutex_lock(&dev_priv->modeset_restore_lock);  in i915_drm_suspend()
626 	dev_priv->modeset_restore = MODESET_SUSPENDED;  in i915_drm_suspend()
627 	mutex_unlock(&dev_priv->modeset_restore_lock);  in i915_drm_suspend()
631 	intel_display_set_init_power(dev_priv, true);  in i915_drm_suspend()
658 	intel_runtime_pm_disable_interrupts(dev_priv);  in i915_drm_suspend()
659 	intel_hpd_cancel_work(dev_priv);  in i915_drm_suspend()
661 	intel_suspend_encoders(dev_priv);  in i915_drm_suspend()
681 	dev_priv->suspend_count++;  in i915_drm_suspend()
683 	intel_display_set_init_power(dev_priv, false);  in i915_drm_suspend()
690 	struct drm_i915_private *dev_priv = drm_dev->dev_private;  in i915_drm_suspend_late()  local
693 	ret = intel_suspend_complete(dev_priv);  in i915_drm_suspend_late()
714 	if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))  in i915_drm_suspend_late()
746 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_drm_resume()  local
766 	intel_runtime_pm_enable_interrupts(dev_priv);  in i915_drm_resume()
771 			atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);  in i915_drm_resume()
779 	spin_lock_irq(&dev_priv->irq_lock);  in i915_drm_resume()
780 	if (dev_priv->display.hpd_irq_setup)  in i915_drm_resume()
781 		dev_priv->display.hpd_irq_setup(dev);  in i915_drm_resume()
782 	spin_unlock_irq(&dev_priv->irq_lock);  in i915_drm_resume()
796 	intel_hpd_init(dev_priv);  in i915_drm_resume()
804 	mutex_lock(&dev_priv->modeset_restore_lock);  in i915_drm_resume()
805 	dev_priv->modeset_restore = MODESET_DONE;  in i915_drm_resume()
806 	mutex_unlock(&dev_priv->modeset_restore_lock);  in i915_drm_resume()
817 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_drm_resume_early()  local
834 	if (IS_VALLEYVIEW(dev_priv))  in i915_drm_resume_early()
835 		ret = vlv_resume_prepare(dev_priv, false);  in i915_drm_resume_early()
843 		ret = bxt_resume_prepare(dev_priv);  in i915_drm_resume_early()
844 	else if (IS_SKYLAKE(dev_priv))  in i915_drm_resume_early()
845 		ret = skl_resume_prepare(dev_priv);  in i915_drm_resume_early()
846 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in i915_drm_resume_early()
847 		hsw_disable_pc8(dev_priv);  in i915_drm_resume_early()
850 	intel_power_domains_init_hw(dev_priv);  in i915_drm_resume_early()
886 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_reset()  local
896 	simulated = dev_priv->gpu_error.stop_rings != 0;  in i915_reset()
903 		dev_priv->gpu_error.stop_rings = 0;  in i915_reset()
911 	if (i915_stop_ring_allow_warn(dev_priv))  in i915_reset()
920 	intel_overlay_reset(dev_priv);  in i915_reset()
938 	dev_priv->gpu_error.reload_in_reset = true;  in i915_reset()
942 	dev_priv->gpu_error.reload_in_reset = false;  in i915_reset()
1057 static int skl_suspend_complete(struct drm_i915_private *dev_priv)  in skl_suspend_complete()  argument
1061 	skl_uninit_cdclk(dev_priv);  in skl_suspend_complete()
1066 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)  in hsw_suspend_complete()  argument
1068 	hsw_enable_pc8(dev_priv);  in hsw_suspend_complete()
1073 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)  in bxt_suspend_complete()  argument
1075 	struct drm_device *dev = dev_priv->dev;  in bxt_suspend_complete()
1081 	bxt_enable_dc9(dev_priv);  in bxt_suspend_complete()
1086 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)  in bxt_resume_prepare()  argument
1088 	struct drm_device *dev = dev_priv->dev;  in bxt_resume_prepare()
1092 	bxt_disable_dc9(dev_priv);  in bxt_resume_prepare()
1105 static int skl_resume_prepare(struct drm_i915_private *dev_priv)  in skl_resume_prepare()  argument
1107 	struct drm_device *dev = dev_priv->dev;  in skl_resume_prepare()
1109 	skl_init_cdclk(dev_priv);  in skl_resume_prepare()
1141 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)  in vlv_save_gunit_s0ix_state()  argument
1143 	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;  in vlv_save_gunit_s0ix_state()
1222 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)  in vlv_restore_gunit_s0ix_state()  argument
1224 	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;  in vlv_restore_gunit_s0ix_state()
1309 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)  in vlv_force_gfx_clock()  argument
1334 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)  in vlv_allow_gt_wake()  argument
1355 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,  in vlv_wait_for_gt_wells()  argument
1385 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)  in vlv_check_no_gt_access()  argument
1394 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)  in vlv_suspend_complete()  argument
1403 	(void)vlv_wait_for_gt_wells(dev_priv, false);  in vlv_suspend_complete()
1408 	vlv_check_no_gt_access(dev_priv);  in vlv_suspend_complete()
1410 	err = vlv_force_gfx_clock(dev_priv, true);  in vlv_suspend_complete()
1414 	err = vlv_allow_gt_wake(dev_priv, false);  in vlv_suspend_complete()
1418 	if (!IS_CHERRYVIEW(dev_priv->dev))  in vlv_suspend_complete()
1419 		vlv_save_gunit_s0ix_state(dev_priv);  in vlv_suspend_complete()
1421 	err = vlv_force_gfx_clock(dev_priv, false);  in vlv_suspend_complete()
1429 	vlv_allow_gt_wake(dev_priv, true);  in vlv_suspend_complete()
1431 	vlv_force_gfx_clock(dev_priv, false);  in vlv_suspend_complete()
1436 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,  in vlv_resume_prepare()  argument
1439 	struct drm_device *dev = dev_priv->dev;  in vlv_resume_prepare()
1448 	ret = vlv_force_gfx_clock(dev_priv, true);  in vlv_resume_prepare()
1450 	if (!IS_CHERRYVIEW(dev_priv->dev))  in vlv_resume_prepare()
1451 		vlv_restore_gunit_s0ix_state(dev_priv);  in vlv_resume_prepare()
1453 	err = vlv_allow_gt_wake(dev_priv, true);  in vlv_resume_prepare()
1457 	err = vlv_force_gfx_clock(dev_priv, false);  in vlv_resume_prepare()
1461 	vlv_check_no_gt_access(dev_priv);  in vlv_resume_prepare()
1475 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_runtime_suspend()  local
1478 	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))  in intel_runtime_suspend()
1507 	i915_gem_release_all_mmaps(dev_priv);  in intel_runtime_suspend()
1513 	intel_runtime_pm_disable_interrupts(dev_priv);  in intel_runtime_suspend()
1515 	ret = intel_suspend_complete(dev_priv);  in intel_runtime_suspend()
1518 		intel_runtime_pm_enable_interrupts(dev_priv);  in intel_runtime_suspend()
1523 	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);  in intel_runtime_suspend()
1525 	dev_priv->pm.suspended = true;  in intel_runtime_suspend()
1550 	assert_forcewakes_inactive(dev_priv);  in intel_runtime_suspend()
1560 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_runtime_resume()  local
1569 	dev_priv->pm.suspended = false;  in intel_runtime_resume()
1573 	if (IS_GEN6(dev_priv))  in intel_runtime_resume()
1577 		ret = bxt_resume_prepare(dev_priv);  in intel_runtime_resume()
1579 		ret = skl_resume_prepare(dev_priv);  in intel_runtime_resume()
1580 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in intel_runtime_resume()
1581 		hsw_disable_pc8(dev_priv);  in intel_runtime_resume()
1582 	else if (IS_VALLEYVIEW(dev_priv))  in intel_runtime_resume()
1583 		ret = vlv_resume_prepare(dev_priv, true);  in intel_runtime_resume()
1592 	intel_runtime_pm_enable_interrupts(dev_priv);  in intel_runtime_resume()
1599 	if (!IS_VALLEYVIEW(dev_priv))  in intel_runtime_resume()
1600 		intel_hpd_init(dev_priv);  in intel_runtime_resume()
1616 static int intel_suspend_complete(struct drm_i915_private *dev_priv)  in intel_suspend_complete()  argument
1620 	if (IS_BROXTON(dev_priv))  in intel_suspend_complete()
1621 		ret = bxt_suspend_complete(dev_priv);  in intel_suspend_complete()
1622 	else if (IS_SKYLAKE(dev_priv))  in intel_suspend_complete()
1623 		ret = skl_suspend_complete(dev_priv);  in intel_suspend_complete()
1624 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in intel_suspend_complete()
1625 		ret = hsw_suspend_complete(dev_priv);  in intel_suspend_complete()
1626 	else if (IS_VALLEYVIEW(dev_priv))  in intel_suspend_complete()
1627 		ret = vlv_suspend_complete(dev_priv);  in intel_suspend_complete()