132 	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);  in describe_obj()  local
147 	for_each_ring(ring, dev_priv, i)  in describe_obj()
207 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_object_list_info()  local
208 	struct i915_address_space *vm = &dev_priv->gtt.base;  in i915_gem_object_list_info()
267 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_stolen_list_info()  local
278 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {  in i915_gem_stolen_list_info()
288 	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {  in i915_gem_stolen_list_info()
398 				   struct drm_i915_private *dev_priv)  in print_batch_pool_stats()  argument
407 	for_each_ring(ring, dev_priv, i) {  in print_batch_pool_stats()
434 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_object_info()  local
438 	struct i915_address_space *vm = &dev_priv->gtt.base;  in i915_gem_object_info()
448 		   dev_priv->mm.object_count,  in i915_gem_object_info()
449 		   dev_priv->mm.object_memory);  in i915_gem_object_info()
452 	count_objects(&dev_priv->mm.bound_list, global_list);  in i915_gem_object_info()
467 	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {  in i915_gem_object_info()
475 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {  in i915_gem_object_info()
497 		   dev_priv->gtt.base.total,  in i915_gem_object_info()
498 		   (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);  in i915_gem_object_info()
501 	print_batch_pool_stats(m, dev_priv);  in i915_gem_object_info()
533 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_gtt_info()  local
543 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {  in i915_gem_gtt_info()
567 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_pageflip_info()  local
602 					   dev_priv->next_seqno,  in i915_gem_pageflip_info()
640 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_batch_pool_info()  local
650 	for_each_ring(ring, dev_priv, i) {  in i915_gem_batch_pool_info()
685 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_request_info()  local
695 	for_each_ring(ring, dev_priv, i) {  in i915_gem_request_info()
743 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_seqno_info()  local
750 	intel_runtime_pm_get(dev_priv);  in i915_gem_seqno_info()
752 	for_each_ring(ring, dev_priv, i)  in i915_gem_seqno_info()
755 	intel_runtime_pm_put(dev_priv);  in i915_gem_seqno_info()
766 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_interrupt_info()  local
773 	intel_runtime_pm_get(dev_priv);  in i915_interrupt_info()
787 		for_each_pipe(dev_priv, pipe)  in i915_interrupt_info()
827 		for_each_pipe(dev_priv, pipe) {  in i915_interrupt_info()
828 			if (!intel_display_power_is_enabled(dev_priv,  in i915_interrupt_info()
874 		for_each_pipe(dev_priv, pipe)  in i915_interrupt_info()
910 		for_each_pipe(dev_priv, pipe)  in i915_interrupt_info()
934 	for_each_ring(ring, dev_priv, i) {  in i915_interrupt_info()
942 	intel_runtime_pm_put(dev_priv);  in i915_interrupt_info()
952 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_fence_regs_info()  local
959 	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);  in i915_gem_fence_regs_info()
960 	for (i = 0; i < dev_priv->num_fence_regs; i++) {  in i915_gem_fence_regs_info()
961 		struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;  in i915_gem_fence_regs_info()
964 			   i, dev_priv->fence_regs[i].pin_count);  in i915_gem_fence_regs_info()
980 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_hws_info()  local
985 	ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];  in i915_hws_info()
1091 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_next_seqno_get()  local
1098 	*val = dev_priv->next_seqno;  in i915_next_seqno_get()
1128 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_frequency_info()  local
1131 	intel_runtime_pm_get(dev_priv);  in i915_frequency_info()
1133 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_frequency_info()
1171 		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);  in i915_frequency_info()
1183 		reqf = intel_gpu_freq(dev_priv, reqf);  in i915_frequency_info()
1202 		cagf = intel_gpu_freq(dev_priv, cagf);  in i915_frequency_info()
1204 		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);  in i915_frequency_info()
1242 			   dev_priv->rps.up_threshold);  in i915_frequency_info()
1251 			   dev_priv->rps.down_threshold);  in i915_frequency_info()
1257 			   intel_gpu_freq(dev_priv, max_freq));  in i915_frequency_info()
1262 			   intel_gpu_freq(dev_priv, max_freq));  in i915_frequency_info()
1268 			   intel_gpu_freq(dev_priv, max_freq));  in i915_frequency_info()
1270 			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));  in i915_frequency_info()
1273 			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));  in i915_frequency_info()
1276 			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));  in i915_frequency_info()
1278 			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));  in i915_frequency_info()
1280 			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));  in i915_frequency_info()
1283 			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));  in i915_frequency_info()
1287 		mutex_lock(&dev_priv->rps.hw_lock);  in i915_frequency_info()
1288 		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);  in i915_frequency_info()
1290 		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);  in i915_frequency_info()
1293 			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));  in i915_frequency_info()
1296 			   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));  in i915_frequency_info()
1299 			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));  in i915_frequency_info()
1302 			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));  in i915_frequency_info()
1305 			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));  in i915_frequency_info()
1309 			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));  in i915_frequency_info()
1310 		mutex_unlock(&dev_priv->rps.hw_lock);  in i915_frequency_info()
1315 	seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);  in i915_frequency_info()
1316 	seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);  in i915_frequency_info()
1317 	seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);  in i915_frequency_info()
1320 	intel_runtime_pm_put(dev_priv);  in i915_frequency_info()
1328 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_hangcheck_info()  local
1339 	intel_runtime_pm_get(dev_priv);  in i915_hangcheck_info()
1341 	for_each_ring(ring, dev_priv, i) {  in i915_hangcheck_info()
1346 	intel_runtime_pm_put(dev_priv);  in i915_hangcheck_info()
1348 	if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {  in i915_hangcheck_info()
1350 			   jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -  in i915_hangcheck_info()
1355 	for_each_ring(ring, dev_priv, i) {  in i915_hangcheck_info()
1375 	struct drm_i915_private *dev_priv = dev->dev_private;  in ironlake_drpc_info()  local
1383 	intel_runtime_pm_get(dev_priv);  in ironlake_drpc_info()
1389 	intel_runtime_pm_put(dev_priv);  in ironlake_drpc_info()
1443 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_forcewake_domains()  local
1447 	spin_lock_irq(&dev_priv->uncore.lock);  in i915_forcewake_domains()
1448 	for_each_fw_domain(fw_domain, dev_priv, i) {  in i915_forcewake_domains()
1453 	spin_unlock_irq(&dev_priv->uncore.lock);  in i915_forcewake_domains()
1462 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_drpc_info()  local
1465 	intel_runtime_pm_get(dev_priv);  in vlv_drpc_info()
1471 	intel_runtime_pm_put(dev_priv);  in vlv_drpc_info()
1502 	struct drm_i915_private *dev_priv = dev->dev_private;  in gen6_drpc_info()  local
1510 	intel_runtime_pm_get(dev_priv);  in gen6_drpc_info()
1512 	spin_lock_irq(&dev_priv->uncore.lock);  in gen6_drpc_info()
1513 	forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;  in gen6_drpc_info()
1514 	spin_unlock_irq(&dev_priv->uncore.lock);  in gen6_drpc_info()
1526 	gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);  in gen6_drpc_info()
1532 	mutex_lock(&dev_priv->rps.hw_lock);  in gen6_drpc_info()
1533 	sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);  in gen6_drpc_info()
1534 	mutex_unlock(&dev_priv->rps.hw_lock);  in gen6_drpc_info()
1536 	intel_runtime_pm_put(dev_priv);  in gen6_drpc_info()
1614 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_frontbuffer_tracking()  local
1617 		   dev_priv->fb_tracking.busy_bits);  in i915_frontbuffer_tracking()
1620 		   dev_priv->fb_tracking.flip_bits);  in i915_frontbuffer_tracking()
1629 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_fbc_status()  local
1636 	intel_runtime_pm_get(dev_priv);  in i915_fbc_status()
1637 	mutex_lock(&dev_priv->fbc.lock);  in i915_fbc_status()
1639 	if (intel_fbc_enabled(dev_priv))  in i915_fbc_status()
1643 			  intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));  in i915_fbc_status()
1645 	if (INTEL_INFO(dev_priv)->gen >= 7)  in i915_fbc_status()
1650 	mutex_unlock(&dev_priv->fbc.lock);  in i915_fbc_status()
1651 	intel_runtime_pm_put(dev_priv);  in i915_fbc_status()
1659 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_fbc_fc_get()  local
1664 	*val = dev_priv->fbc.false_color;  in i915_fbc_fc_get()
1672 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_fbc_fc_set()  local
1678 	mutex_lock(&dev_priv->fbc.lock);  in i915_fbc_fc_set()
1681 	dev_priv->fbc.false_color = val;  in i915_fbc_fc_set()
1687 	mutex_unlock(&dev_priv->fbc.lock);  in i915_fbc_fc_set()
1699 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ips_status()  local
1706 	intel_runtime_pm_get(dev_priv);  in i915_ips_status()
1720 	intel_runtime_pm_put(dev_priv);  in i915_ips_status()
1729 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_sr_status()  local
1732 	intel_runtime_pm_get(dev_priv);  in i915_sr_status()
1746 	intel_runtime_pm_put(dev_priv);  in i915_sr_status()
1758 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_emon_status()  local
1769 	temp = i915_mch_val(dev_priv);  in i915_emon_status()
1770 	chipset = i915_chipset_val(dev_priv);  in i915_emon_status()
1771 	gfx = i915_gfx_val(dev_priv);  in i915_emon_status()
1786 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_freq_table()  local
1796 	intel_runtime_pm_get(dev_priv);  in i915_ring_freq_table()
1798 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_ring_freq_table()
1800 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_ring_freq_table()
1807 			dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;  in i915_ring_freq_table()
1809 			dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;  in i915_ring_freq_table()
1811 		min_gpu_freq = dev_priv->rps.min_freq_softlimit;  in i915_ring_freq_table()
1812 		max_gpu_freq = dev_priv->rps.max_freq_softlimit;  in i915_ring_freq_table()
1819 		sandybridge_pcode_read(dev_priv,  in i915_ring_freq_table()
1823 			   intel_gpu_freq(dev_priv, (gpu_freq *  in i915_ring_freq_table()
1829 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_ring_freq_table()
1832 	intel_runtime_pm_put(dev_priv);  in i915_ring_freq_table()
1840 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_opregion()  local
1841 	struct intel_opregion *opregion = &dev_priv->opregion;  in i915_opregion()
1873 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_framebuffer_info()  local
1875 	ifbdev = dev_priv->fbdev;  in i915_gem_framebuffer_info()
1922 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_context_status()  local
1931 	list_for_each_entry(ctx, &dev_priv->context_list, link) {  in i915_context_status()
1938 		for_each_ring(ring, dev_priv, i) {  in i915_context_status()
1946 			for_each_ring(ring, dev_priv, i) {  in i915_context_status()
2019 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_dump_lrc()  local
2033 	list_for_each_entry(ctx, &dev_priv->context_list, link) {  in i915_dump_lrc()
2034 		for_each_ring(ring, dev_priv, i) {  in i915_dump_lrc()
2050 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_execlists()  local
2070 	intel_runtime_pm_get(dev_priv);  in i915_execlists()
2072 	for_each_ring(ring, dev_priv, ring_id) {  in i915_execlists()
2123 	intel_runtime_pm_put(dev_priv);  in i915_execlists()
2157 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_swizzle_info()  local
2163 	intel_runtime_pm_get(dev_priv);  in i915_swizzle_info()
2166 		   swizzle_string(dev_priv->mm.bit_6_swizzle_x));  in i915_swizzle_info()
2168 		   swizzle_string(dev_priv->mm.bit_6_swizzle_y));  in i915_swizzle_info()
2198 	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)  in i915_swizzle_info()
2201 	intel_runtime_pm_put(dev_priv);  in i915_swizzle_info()
2230 	struct drm_i915_private *dev_priv = dev->dev_private;  in gen8_ppgtt_info()  local
2232 	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;  in gen8_ppgtt_info()
2238 	for_each_ring(ring, dev_priv, unused) {  in gen8_ppgtt_info()
2251 	struct drm_i915_private *dev_priv = dev->dev_private;  in gen6_ppgtt_info()  local
2258 	for_each_ring(ring, dev_priv, i) {  in gen6_ppgtt_info()
2266 	if (dev_priv->mm.aliasing_ppgtt) {  in gen6_ppgtt_info()
2267 		struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;  in gen6_ppgtt_info()
2282 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ppgtt_info()  local
2288 	intel_runtime_pm_get(dev_priv);  in i915_ppgtt_info()
2311 	intel_runtime_pm_put(dev_priv);  in i915_ppgtt_info()
2333 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_rps_boost_info()  local
2336 	seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);  in i915_rps_boost_info()
2337 	seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);  in i915_rps_boost_info()
2338 	seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));  in i915_rps_boost_info()
2340 		   intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),  in i915_rps_boost_info()
2341 		   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),  in i915_rps_boost_info()
2342 		   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),  in i915_rps_boost_info()
2343 		   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),  in i915_rps_boost_info()
2344 		   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));  in i915_rps_boost_info()
2345 	spin_lock(&dev_priv->rps.client_lock);  in i915_rps_boost_info()
2360 		   dev_priv->rps.semaphores.boosts,  in i915_rps_boost_info()
2361 		   list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");  in i915_rps_boost_info()
2363 		   dev_priv->rps.mmioflips.boosts,  in i915_rps_boost_info()
2364 		   list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");  in i915_rps_boost_info()
2365 	seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);  in i915_rps_boost_info()
2366 	spin_unlock(&dev_priv->rps.client_lock);  in i915_rps_boost_info()
2375 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_llc()  local
2379 	seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);  in i915_llc()
2387 	struct drm_i915_private *dev_priv = node->minor->dev->dev_private;  in i915_guc_load_status_info()  local
2388 	struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;  in i915_guc_load_status_info()
2391 	if (!HAS_GUC_UCODE(dev_priv->dev))  in i915_guc_load_status_info()
2423 				 struct drm_i915_private *dev_priv,  in i915_guc_client_info()  argument
2441 	for_each_ring(ring, dev_priv, i) {  in i915_guc_client_info()
2454 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_guc_info()  local
2461 	if (!HAS_GUC_SCHED(dev_priv->dev))  in i915_guc_info()
2465 	spin_lock(&dev_priv->guc.host2guc_lock);  in i915_guc_info()
2466 	guc = dev_priv->guc;  in i915_guc_info()
2472 	spin_unlock(&dev_priv->guc.host2guc_lock);  in i915_guc_info()
2481 	for_each_ring(ring, dev_priv, i) {  in i915_guc_info()
2490 	i915_guc_client_info(m, dev_priv, &client);  in i915_guc_info()
2501 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_guc_log_dump()  local
2502 	struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;  in i915_guc_log_dump()
2529 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_edp_psr_status()  local
2540 	intel_runtime_pm_get(dev_priv);  in i915_edp_psr_status()
2542 	mutex_lock(&dev_priv->psr.lock);  in i915_edp_psr_status()
2543 	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));  in i915_edp_psr_status()
2544 	seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));  in i915_edp_psr_status()
2545 	seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));  in i915_edp_psr_status()
2546 	seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));  in i915_edp_psr_status()
2548 		   dev_priv->psr.busy_frontbuffer_bits);  in i915_edp_psr_status()
2550 		   yesno(work_busy(&dev_priv->psr.work.work)));  in i915_edp_psr_status()
2555 		for_each_pipe(dev_priv, pipe) {  in i915_edp_psr_status()
2566 		for_each_pipe(dev_priv, pipe) {  in i915_edp_psr_status()
2580 	mutex_unlock(&dev_priv->psr.lock);  in i915_edp_psr_status()
2582 	intel_runtime_pm_put(dev_priv);  in i915_edp_psr_status()
2630 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_energy_uJ()  local
2637 	intel_runtime_pm_get(dev_priv);  in i915_energy_uJ()
2645 	intel_runtime_pm_put(dev_priv);  in i915_energy_uJ()
2656 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_runtime_pm_status()  local
2663 	seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));  in i915_runtime_pm_status()
2665 		   yesno(!intel_irqs_enabled(dev_priv)));  in i915_runtime_pm_status()
2751 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_power_domain_info()  local
2752 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in i915_power_domain_info()
2920 	struct drm_i915_private *dev_priv = dev->dev_private;  in cursor_active()  local
2933 	struct drm_i915_private *dev_priv = dev->dev_private;  in cursor_position()  local
2953 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_display_info()  local
2957 	intel_runtime_pm_get(dev_priv);  in i915_display_info()
2995 	intel_runtime_pm_put(dev_priv);  in i915_display_info()
3004 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_semaphore_status()  local
3017 	intel_runtime_pm_get(dev_priv);  in i915_semaphore_status()
3023 		page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);  in i915_semaphore_status()
3026 		for_each_ring(ring, dev_priv, i) {  in i915_semaphore_status()
3051 		for_each_ring(ring, dev_priv, i)  in i915_semaphore_status()
3059 	for_each_ring(ring, dev_priv, i) {  in i915_semaphore_status()
3067 	intel_runtime_pm_put(dev_priv);  in i915_semaphore_status()
3076 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_shared_dplls_info()  local
3080 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {  in i915_shared_dplls_info()
3081 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];  in i915_shared_dplls_info()
3105 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_wa_registers()  local
3111 	intel_runtime_pm_get(dev_priv);  in i915_wa_registers()
3113 	seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);  in i915_wa_registers()
3114 	for (i = 0; i < dev_priv->workarounds.count; ++i) {  in i915_wa_registers()
3118 		addr = dev_priv->workarounds.reg[i].addr;  in i915_wa_registers()
3119 		mask = dev_priv->workarounds.reg[i].mask;  in i915_wa_registers()
3120 		value = dev_priv->workarounds.reg[i].value;  in i915_wa_registers()
3127 	intel_runtime_pm_put(dev_priv);  in i915_wa_registers()
3137 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ddb_info()  local
3148 	ddb = &dev_priv->wm.skl_hw.ddb;  in i915_ddb_info()
3152 	for_each_pipe(dev_priv, pipe) {  in i915_ddb_info()
3155 		for_each_plane(dev_priv, pipe, plane) {  in i915_ddb_info()
3176 	struct drm_i915_private *dev_priv = dev->dev_private;  in drrs_status_per_crtc()  local
3177 	struct i915_drrs *drrs = &dev_priv->drrs;  in drrs_status_per_crtc()
3202 	if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)  in drrs_status_per_crtc()
3204 	else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)  in drrs_status_per_crtc()
3206 	else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)  in drrs_status_per_crtc()
3312 	struct drm_i915_private *dev_priv = info->dev->dev_private;  in i915_pipe_crc_open()  local
3313 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];  in i915_pipe_crc_open()
3336 	struct drm_i915_private *dev_priv = info->dev->dev_private;  in i915_pipe_crc_release()  local
3337 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];  in i915_pipe_crc_release()
3364 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_pipe_crc_read()  local
3365 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];  in i915_pipe_crc_read()
3497 	struct drm_i915_private *dev_priv = dev->dev_private;  in display_crc_ctl_show()  local
3502 			   pipe_crc_source_name(dev_priv->pipe_crc[i].source));  in display_crc_ctl_show()
3591 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_pipe_crc_ctl_reg()  local
3662 	struct drm_i915_private *dev_priv = dev->dev_private;  in i9xx_pipe_crc_ctl_reg()  local
3736 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_undo_pipe_scramble_reset()  local
3761 	struct drm_i915_private *dev_priv = dev->dev_private;  in g4x_undo_pipe_scramble_reset()  local
3804 	struct drm_i915_private *dev_priv = dev->dev_private;  in hsw_trans_edp_pipe_A_crc_wa()  local
3806 		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);  in hsw_trans_edp_pipe_A_crc_wa()
3872 	struct drm_i915_private *dev_priv = dev->dev_private;  in pipe_crc_set_source()  local
3873 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];  in pipe_crc_set_source()
3886 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {  in pipe_crc_set_source()
3943 			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);  in pipe_crc_set_source()
4369 	struct drm_i915_private *dev_priv = dev->dev_private;  in pri_wm_latency_show()  local
4373 		latencies = dev_priv->wm.skl_latency;  in pri_wm_latency_show()
4385 	struct drm_i915_private *dev_priv = dev->dev_private;  in spr_wm_latency_show()  local
4389 		latencies = dev_priv->wm.skl_latency;  in spr_wm_latency_show()
4401 	struct drm_i915_private *dev_priv = dev->dev_private;  in cur_wm_latency_show()  local
4405 		latencies = dev_priv->wm.skl_latency;  in cur_wm_latency_show()
4492 	struct drm_i915_private *dev_priv = dev->dev_private;  in pri_wm_latency_write()  local
4496 		latencies = dev_priv->wm.skl_latency;  in pri_wm_latency_write()
4508 	struct drm_i915_private *dev_priv = dev->dev_private;  in spr_wm_latency_write()  local
4512 		latencies = dev_priv->wm.skl_latency;  in spr_wm_latency_write()
4524 	struct drm_i915_private *dev_priv = dev->dev_private;  in cur_wm_latency_write()  local
4528 		latencies = dev_priv->wm.skl_latency;  in cur_wm_latency_write()
4566 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_wedged_get()  local
4568 	*val = atomic_read(&dev_priv->gpu_error.reset_counter);  in i915_wedged_get()
4577 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_wedged_set()  local
4587 	if (i915_reset_in_progress(&dev_priv->gpu_error))  in i915_wedged_set()
4590 	intel_runtime_pm_get(dev_priv);  in i915_wedged_set()
4595 	intel_runtime_pm_put(dev_priv);  in i915_wedged_set()
4608 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_stop_get()  local
4610 	*val = dev_priv->gpu_error.stop_rings;  in i915_ring_stop_get()
4619 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_stop_set()  local
4628 	dev_priv->gpu_error.stop_rings = val;  in i915_ring_stop_set()
4642 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_missed_irq_get()  local
4644 	*val = dev_priv->gpu_error.missed_irq_rings;  in i915_ring_missed_irq_get()
4652 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_missed_irq_set()  local
4659 	dev_priv->gpu_error.missed_irq_rings = val;  in i915_ring_missed_irq_set()
4673 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_test_irq_get()  local
4675 	*val = dev_priv->gpu_error.test_irq_rings;  in i915_ring_test_irq_get()
4684 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_test_irq_set()  local
4694 	dev_priv->gpu_error.test_irq_rings = val;  in i915_ring_test_irq_set()
4724 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_drop_caches_set()  local
4745 		i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);  in i915_drop_caches_set()
4748 		i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);  in i915_drop_caches_set()
4764 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_max_freq_get()  local
4770 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_max_freq_get()
4772 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_max_freq_get()
4776 	*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);  in i915_max_freq_get()
4777 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_max_freq_get()
4786 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_max_freq_set()  local
4793 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_max_freq_set()
4797 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_max_freq_set()
4804 	val = intel_freq_opcode(dev_priv, val);  in i915_max_freq_set()
4806 	hw_max = dev_priv->rps.max_freq;  in i915_max_freq_set()
4807 	hw_min = dev_priv->rps.min_freq;  in i915_max_freq_set()
4809 	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {  in i915_max_freq_set()
4810 		mutex_unlock(&dev_priv->rps.hw_lock);  in i915_max_freq_set()
4814 	dev_priv->rps.max_freq_softlimit = val;  in i915_max_freq_set()
4818 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_max_freq_set()
4831 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_min_freq_get()  local
4837 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_min_freq_get()
4839 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_min_freq_get()
4843 	*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);  in i915_min_freq_get()
4844 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_min_freq_get()
4853 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_min_freq_set()  local
4860 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_min_freq_set()
4864 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_min_freq_set()
4871 	val = intel_freq_opcode(dev_priv, val);  in i915_min_freq_set()
4873 	hw_max = dev_priv->rps.max_freq;  in i915_min_freq_set()
4874 	hw_min = dev_priv->rps.min_freq;  in i915_min_freq_set()
4876 	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {  in i915_min_freq_set()
4877 		mutex_unlock(&dev_priv->rps.hw_lock);  in i915_min_freq_set()
4881 	dev_priv->rps.min_freq_softlimit = val;  in i915_min_freq_set()
4885 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_min_freq_set()
4898 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_cache_sharing_get()  local
4908 	intel_runtime_pm_get(dev_priv);  in i915_cache_sharing_get()
4912 	intel_runtime_pm_put(dev_priv);  in i915_cache_sharing_get()
4913 	mutex_unlock(&dev_priv->dev->struct_mutex);  in i915_cache_sharing_get()
4924 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_cache_sharing_set()  local
4933 	intel_runtime_pm_get(dev_priv);  in i915_cache_sharing_set()
4942 	intel_runtime_pm_put(dev_priv);  in i915_cache_sharing_set()
4961 	struct drm_i915_private *dev_priv = dev->dev_private;  in cherryview_sseu_device_status()  local
4993 	struct drm_i915_private *dev_priv = dev->dev_private;  in gen9_sseu_device_status()  local
5058 	struct drm_i915_private *dev_priv = dev->dev_private;  in broadwell_sseu_device_status()  local
5133 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_forcewake_open()  local
5138 	intel_runtime_pm_get(dev_priv);  in i915_forcewake_open()
5139 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);  in i915_forcewake_open()
5147 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_forcewake_release()  local
5152 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);  in i915_forcewake_release()
5153 	intel_runtime_pm_put(dev_priv);  in i915_forcewake_release()
5279 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_display_crc_init()  local
5282 	for_each_pipe(dev_priv, pipe) {  in intel_display_crc_init()
5283 		struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];  in intel_display_crc_init()