Lines Matching refs:PIPE_CRC_ENABLE
3522 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; in i8xx_pipe_crc_ctl_reg()
3602 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; in vlv_pipe_crc_ctl_reg()
3605 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; in vlv_pipe_crc_ctl_reg()
3609 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; in vlv_pipe_crc_ctl_reg()
3615 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; in vlv_pipe_crc_ctl_reg()
3673 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; in i9xx_pipe_crc_ctl_reg()
3678 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; in i9xx_pipe_crc_ctl_reg()
3683 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; in i9xx_pipe_crc_ctl_reg()
3689 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; in i9xx_pipe_crc_ctl_reg()
3695 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; in i9xx_pipe_crc_ctl_reg()
3784 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; in ilk_pipe_crc_ctl_reg()
3787 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; in ilk_pipe_crc_ctl_reg()
3790 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; in ilk_pipe_crc_ctl_reg()
3848 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; in ivb_pipe_crc_ctl_reg()
3851 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; in ivb_pipe_crc_ctl_reg()
3857 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; in ivb_pipe_crc_ctl_reg()