Lines Matching refs:REG32
416 #define REG32(address, ...) \ macro
427 REG32(addr), REG32(addr + sizeof(u32))
442 REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
445 REG32(GEN7_3DPRIM_END_OFFSET),
446 REG32(GEN7_3DPRIM_START_VERTEX),
447 REG32(GEN7_3DPRIM_VERTEX_COUNT),
448 REG32(GEN7_3DPRIM_INSTANCE_COUNT),
449 REG32(GEN7_3DPRIM_START_INSTANCE),
450 REG32(GEN7_3DPRIM_BASE_VERTEX),
451 REG32(GEN7_GPGPU_DISPATCHDIMX),
452 REG32(GEN7_GPGPU_DISPATCHDIMY),
453 REG32(GEN7_GPGPU_DISPATCHDIMZ),
462 REG32(GEN7_SO_WRITE_OFFSET(0)),
463 REG32(GEN7_SO_WRITE_OFFSET(1)),
464 REG32(GEN7_SO_WRITE_OFFSET(2)),
465 REG32(GEN7_SO_WRITE_OFFSET(3)),
466 REG32(GEN7_L3SQCREG1),
467 REG32(GEN7_L3CNTLREG2),
468 REG32(GEN7_L3CNTLREG3),
469 REG32(HSW_SCRATCH1,
472 REG32(HSW_ROW_CHICKEN3,
479 REG32(BCS_SWCTRL),
483 REG32(FORCEWAKE_MT),
484 REG32(DERRMR),
485 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
486 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
487 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
491 REG32(FORCEWAKE_MT),
492 REG32(DERRMR),
496 #undef REG32