Lines Matching refs:u16
23 u16 pixel_clock;
56 u16 pixel_clock;
62 u16 hsync_offset_hi:2;
63 u16 hsync_pulse_width_lo:8;
64 u16 hsync_pulse_width_hi:2;
65 u16 hsync_positive:1;
66 u16 rsvd_1:3;
68 u16 vactive_hi:4;
69 u16 vblank_lo:8;
70 u16 vblank_hi:4;
71 u16 vsync_offset_lo:4;
72 u16 vsync_offset_hi:2;
73 u16 vsync_pulse_width_lo:4;
74 u16 vsync_pulse_width_hi:2;
75 u16 vsync_positive:1;
76 u16 rsvd_2:3;
87 u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
90 u16 Panel_MIPI_Display_Descriptor;
116 u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
120 u16 Panel_MIPI_Display_Descriptor;
140 u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
142 u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
144 u16 SupportedVideoTransferMode:2; /*0: Non-burst only */
147 u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/
148 u16 DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/
149 u16 ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/
150 u16 BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */
151 u16 Rsvd:5;/*5 bits,00000b */
153 u16 panel_receiver;
192 u16 Panel_MIPI_Display_Descriptor;
193 u16 Panel_MIPI_Receiver_Descriptor;
194 u16 Panel_Backlight_Inverter_Descriptor;
208 u16 Panel_Backlight_Inverter_Descriptor;
209 u16 Panel_MIPI_Display_Descriptor;