Lines Matching refs:res
143 static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id) in vp_reg_read() argument
145 return readl(res->vp_regs + reg_id); in vp_reg_read()
148 static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id, in vp_reg_write() argument
151 writel(val, res->vp_regs + reg_id); in vp_reg_write()
154 static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id, in vp_reg_writemask() argument
157 u32 old = vp_reg_read(res, reg_id); in vp_reg_writemask()
160 writel(val, res->vp_regs + reg_id); in vp_reg_writemask()
163 static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id) in mixer_reg_read() argument
165 return readl(res->mixer_regs + reg_id); in mixer_reg_read()
168 static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id, in mixer_reg_write() argument
171 writel(val, res->mixer_regs + reg_id); in mixer_reg_write()
174 static inline void mixer_reg_writemask(struct mixer_resources *res, in mixer_reg_writemask() argument
177 u32 old = mixer_reg_read(res, reg_id); in mixer_reg_writemask()
180 writel(val, res->mixer_regs + reg_id); in mixer_reg_writemask()
250 static inline void vp_filter_set(struct mixer_resources *res, in vp_filter_set() argument
258 vp_reg_write(res, reg_id, val); in vp_filter_set()
262 static void vp_default_filter(struct mixer_resources *res) in vp_default_filter() argument
264 vp_filter_set(res, VP_POLY8_Y0_LL, in vp_default_filter()
266 vp_filter_set(res, VP_POLY4_Y0_LL, in vp_default_filter()
268 vp_filter_set(res, VP_POLY4_C0_LL, in vp_default_filter()
274 struct mixer_resources *res = &ctx->mixer_res; in mixer_vsync_set_update() local
277 mixer_reg_writemask(res, MXR_STATUS, enable ? in mixer_vsync_set_update()
281 vp_reg_write(res, VP_SHADOW_UPDATE, enable ? in mixer_vsync_set_update()
287 struct mixer_resources *res = &ctx->mixer_res; in mixer_cfg_scan() local
308 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK); in mixer_cfg_scan()
313 struct mixer_resources *res = &ctx->mixer_res; in mixer_cfg_rgb_fmt() local
322 mixer_reg_write(res, MXR_CM_COEFF_Y, in mixer_cfg_rgb_fmt()
325 mixer_reg_write(res, MXR_CM_COEFF_CB, in mixer_cfg_rgb_fmt()
327 mixer_reg_write(res, MXR_CM_COEFF_CR, in mixer_cfg_rgb_fmt()
331 mixer_reg_write(res, MXR_CM_COEFF_Y, in mixer_cfg_rgb_fmt()
334 mixer_reg_write(res, MXR_CM_COEFF_CB, in mixer_cfg_rgb_fmt()
336 mixer_reg_write(res, MXR_CM_COEFF_CR, in mixer_cfg_rgb_fmt()
340 mixer_reg_write(res, MXR_CM_COEFF_Y, in mixer_cfg_rgb_fmt()
343 mixer_reg_write(res, MXR_CM_COEFF_CB, in mixer_cfg_rgb_fmt()
345 mixer_reg_write(res, MXR_CM_COEFF_CR, in mixer_cfg_rgb_fmt()
349 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK); in mixer_cfg_rgb_fmt()
355 struct mixer_resources *res = &ctx->mixer_res; in mixer_cfg_layer() local
360 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); in mixer_cfg_layer()
363 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); in mixer_cfg_layer()
367 vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON); in mixer_cfg_layer()
368 mixer_reg_writemask(res, MXR_CFG, val, in mixer_cfg_layer()
372 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(0), val, in mixer_cfg_layer()
382 struct mixer_resources *res = &ctx->mixer_res; in mixer_run() local
384 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN); in mixer_run()
389 struct mixer_resources *res = &ctx->mixer_res; in mixer_stop() local
392 mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN); in mixer_stop()
394 while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) && in mixer_stop()
402 struct mixer_resources *res = &ctx->mixer_res; in vp_video_buffer() local
443 spin_lock_irqsave(&res->reg_slock, flags); in vp_video_buffer()
448 vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP); in vp_video_buffer()
453 vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK); in vp_video_buffer()
456 vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) | in vp_video_buffer()
459 vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) | in vp_video_buffer()
462 vp_reg_write(res, VP_SRC_WIDTH, plane->src_w); in vp_video_buffer()
463 vp_reg_write(res, VP_SRC_HEIGHT, plane->src_h); in vp_video_buffer()
464 vp_reg_write(res, VP_SRC_H_POSITION, in vp_video_buffer()
466 vp_reg_write(res, VP_SRC_V_POSITION, plane->src_y); in vp_video_buffer()
468 vp_reg_write(res, VP_DST_WIDTH, plane->crtc_w); in vp_video_buffer()
469 vp_reg_write(res, VP_DST_H_POSITION, plane->crtc_x); in vp_video_buffer()
471 vp_reg_write(res, VP_DST_HEIGHT, plane->crtc_h / 2); in vp_video_buffer()
472 vp_reg_write(res, VP_DST_V_POSITION, plane->crtc_y / 2); in vp_video_buffer()
474 vp_reg_write(res, VP_DST_HEIGHT, plane->crtc_h); in vp_video_buffer()
475 vp_reg_write(res, VP_DST_V_POSITION, plane->crtc_y); in vp_video_buffer()
478 vp_reg_write(res, VP_H_RATIO, plane->h_ratio); in vp_video_buffer()
479 vp_reg_write(res, VP_V_RATIO, plane->v_ratio); in vp_video_buffer()
481 vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE); in vp_video_buffer()
484 vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]); in vp_video_buffer()
485 vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]); in vp_video_buffer()
486 vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]); in vp_video_buffer()
487 vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]); in vp_video_buffer()
495 spin_unlock_irqrestore(&res->reg_slock, flags); in vp_video_buffer()
503 struct mixer_resources *res = &ctx->mixer_res; in mixer_layer_update() local
505 mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE); in mixer_layer_update()
535 struct mixer_resources *res = &ctx->mixer_res; in mixer_graph_buffer() local
589 spin_lock_irqsave(&res->reg_slock, flags); in mixer_graph_buffer()
593 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), in mixer_graph_buffer()
597 mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), in mixer_graph_buffer()
605 mixer_reg_write(res, MXR_RESOLUTION, val); in mixer_graph_buffer()
612 mixer_reg_write(res, MXR_GRAPHIC_WH(win), val); in mixer_graph_buffer()
617 mixer_reg_write(res, MXR_GRAPHIC_SXY(win), val); in mixer_graph_buffer()
622 mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val); in mixer_graph_buffer()
625 mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr); in mixer_graph_buffer()
639 spin_unlock_irqrestore(&res->reg_slock, flags); in mixer_graph_buffer()
646 struct mixer_resources *res = &ctx->mixer_res; in vp_win_reset() local
649 vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING); in vp_win_reset()
652 if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING) in vp_win_reset()
661 struct mixer_resources *res = &ctx->mixer_res; in mixer_win_reset() local
665 spin_lock_irqsave(&res->reg_slock, flags); in mixer_win_reset()
668 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK); in mixer_win_reset()
671 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK); in mixer_win_reset()
674 mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST, in mixer_win_reset()
687 mixer_reg_write(res, MXR_LAYER_CFG, val); in mixer_win_reset()
690 mixer_reg_write(res, MXR_BG_COLOR0, 0x008080); in mixer_win_reset()
691 mixer_reg_write(res, MXR_BG_COLOR1, 0x008080); in mixer_win_reset()
692 mixer_reg_write(res, MXR_BG_COLOR2, 0x008080); in mixer_win_reset()
700 mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val); in mixer_win_reset()
705 mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val); in mixer_win_reset()
709 mixer_reg_write(res, MXR_VIDEO_CFG, val); in mixer_win_reset()
714 vp_default_filter(res); in mixer_win_reset()
718 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE); in mixer_win_reset()
719 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE); in mixer_win_reset()
721 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE); in mixer_win_reset()
724 spin_unlock_irqrestore(&res->reg_slock, flags); in mixer_win_reset()
730 struct mixer_resources *res = &ctx->mixer_res; in mixer_irq_handler() local
734 spin_lock(&res->reg_slock); in mixer_irq_handler()
737 val = mixer_reg_read(res, MXR_INT_STATUS); in mixer_irq_handler()
747 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0)); in mixer_irq_handler()
748 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0)); in mixer_irq_handler()
752 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1)); in mixer_irq_handler()
753 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1)); in mixer_irq_handler()
777 mixer_reg_write(res, MXR_INT_STATUS, val); in mixer_irq_handler()
779 spin_unlock(&res->reg_slock); in mixer_irq_handler()
788 struct resource *res; in mixer_resources_init() local
810 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 0); in mixer_resources_init()
811 if (res == NULL) { in mixer_resources_init()
816 mixer_res->mixer_regs = devm_ioremap(dev, res->start, in mixer_resources_init()
817 resource_size(res)); in mixer_resources_init()
823 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_IRQ, 0); in mixer_resources_init()
824 if (res == NULL) { in mixer_resources_init()
829 ret = devm_request_irq(dev, res->start, mixer_irq_handler, in mixer_resources_init()
835 mixer_res->irq = res->start; in mixer_resources_init()
844 struct resource *res; in vp_resources_init() local
869 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1); in vp_resources_init()
870 if (res == NULL) { in vp_resources_init()
875 mixer_res->vp_regs = devm_ioremap(dev, res->start, in vp_resources_init()
876 resource_size(res)); in vp_resources_init()
926 struct mixer_resources *res = &mixer_ctx->mixer_res; in mixer_enable_vblank() local
933 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); in mixer_enable_vblank()
934 mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); in mixer_enable_vblank()
942 struct mixer_resources *res = &mixer_ctx->mixer_res; in mixer_disable_vblank() local
950 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); in mixer_disable_vblank()
951 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC); in mixer_disable_vblank()
974 struct mixer_resources *res = &mixer_ctx->mixer_res; in mixer_disable_plane() local
982 spin_lock_irqsave(&res->reg_slock, flags); in mixer_disable_plane()
988 spin_unlock_irqrestore(&res->reg_slock, flags); in mixer_disable_plane()
1022 struct mixer_resources *res = &ctx->mixer_res; in mixer_enable() local
1030 ret = clk_prepare_enable(res->mixer); in mixer_enable()
1035 ret = clk_prepare_enable(res->hdmi); in mixer_enable()
1041 ret = clk_prepare_enable(res->vp); in mixer_enable()
1048 ret = clk_prepare_enable(res->sclk_mixer); in mixer_enable()
1060 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); in mixer_enable()
1063 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); in mixer_enable()
1064 mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); in mixer_enable()
1072 struct mixer_resources *res = &ctx->mixer_res; in mixer_disable() local
1086 clk_disable_unprepare(res->hdmi); in mixer_disable()
1087 clk_disable_unprepare(res->mixer); in mixer_disable()
1089 clk_disable_unprepare(res->vp); in mixer_disable()
1091 clk_disable_unprepare(res->sclk_mixer); in mixer_disable()