210 	u32 val;  in fimd_enable_vblank()  local
216 		val = readl(ctx->regs + VIDINTCON0);  in fimd_enable_vblank()
218 		val |= VIDINTCON0_INT_ENABLE;  in fimd_enable_vblank()
221 			val |= VIDINTCON0_INT_I80IFDONE;  in fimd_enable_vblank()
222 			val |= VIDINTCON0_INT_SYSMAINCON;  in fimd_enable_vblank()
223 			val &= ~VIDINTCON0_INT_SYSSUBCON;  in fimd_enable_vblank()
225 			val |= VIDINTCON0_INT_FRAME;  in fimd_enable_vblank()
227 			val &= ~VIDINTCON0_FRAMESEL0_MASK;  in fimd_enable_vblank()
228 			val |= VIDINTCON0_FRAMESEL0_VSYNC;  in fimd_enable_vblank()
229 			val &= ~VIDINTCON0_FRAMESEL1_MASK;  in fimd_enable_vblank()
230 			val |= VIDINTCON0_FRAMESEL1_NONE;  in fimd_enable_vblank()
233 		writel(val, ctx->regs + VIDINTCON0);  in fimd_enable_vblank()
242 	u32 val;  in fimd_disable_vblank()  local
248 		val = readl(ctx->regs + VIDINTCON0);  in fimd_disable_vblank()
250 		val &= ~VIDINTCON0_INT_ENABLE;  in fimd_disable_vblank()
253 			val &= ~VIDINTCON0_INT_I80IFDONE;  in fimd_disable_vblank()
254 			val &= ~VIDINTCON0_INT_SYSMAINCON;  in fimd_disable_vblank()
255 			val &= ~VIDINTCON0_INT_SYSSUBCON;  in fimd_disable_vblank()
257 			val &= ~VIDINTCON0_INT_FRAME;  in fimd_disable_vblank()
259 		writel(val, ctx->regs + VIDINTCON0);  in fimd_disable_vblank()
285 	u32 val = readl(ctx->regs + WINCON(win));  in fimd_enable_video_output()  local
288 		val |= WINCONx_ENWIN;  in fimd_enable_video_output()
290 		val &= ~WINCONx_ENWIN;  in fimd_enable_video_output()
292 	writel(val, ctx->regs + WINCON(win));  in fimd_enable_video_output()
299 	u32 val = readl(ctx->regs + SHADOWCON);  in fimd_enable_shadow_channel_path()  local
302 		val |= SHADOWCON_CHx_ENABLE(win);  in fimd_enable_shadow_channel_path()
304 		val &= ~SHADOWCON_CHx_ENABLE(win);  in fimd_enable_shadow_channel_path()
306 	writel(val, ctx->regs + SHADOWCON);  in fimd_enable_shadow_channel_path()
324 		u32 val = readl(ctx->regs + WINCON(win));  in fimd_clear_channels()  local
326 		if (val & WINCONx_ENWIN) {  in fimd_clear_channels()
385 	u32 val, clkdiv;  in fimd_commit()  local
395 		val = ctx->i80ifcon | I80IFEN_ENABLE;  in fimd_commit()
396 		writel(val, timing_base + I80IFCONFAx(0));  in fimd_commit()
427 		val = VIDTCON0_VBPD(vbpd - 1) |  in fimd_commit()
430 		writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);  in fimd_commit()
437 		val = VIDTCON1_HBPD(hbpd - 1) |  in fimd_commit()
440 		writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);  in fimd_commit()
456 	val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |  in fimd_commit()
460 	writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);  in fimd_commit()
466 	val = ctx->vidcon0;  in fimd_commit()
467 	val |= VIDCON0_ENVID | VIDCON0_ENVID_F;  in fimd_commit()
470 		val |= VIDCON0_CLKSEL_LCD;  in fimd_commit()
474 		val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;  in fimd_commit()
476 	writel(val, ctx->regs + VIDCON0);  in fimd_commit()
483 	unsigned long val;  in fimd_win_set_pixfmt()  local
485 	val = WINCONx_ENWIN;  in fimd_win_set_pixfmt()
498 		val |= WINCON0_BPPMODE_8BPP_PALETTE;  in fimd_win_set_pixfmt()
499 		val |= WINCONx_BURSTLEN_8WORD;  in fimd_win_set_pixfmt()
500 		val |= WINCONx_BYTSWP;  in fimd_win_set_pixfmt()
503 		val |= WINCON0_BPPMODE_16BPP_1555;  in fimd_win_set_pixfmt()
504 		val |= WINCONx_HAWSWP;  in fimd_win_set_pixfmt()
505 		val |= WINCONx_BURSTLEN_16WORD;  in fimd_win_set_pixfmt()
508 		val |= WINCON0_BPPMODE_16BPP_565;  in fimd_win_set_pixfmt()
509 		val |= WINCONx_HAWSWP;  in fimd_win_set_pixfmt()
510 		val |= WINCONx_BURSTLEN_16WORD;  in fimd_win_set_pixfmt()
513 		val |= WINCON0_BPPMODE_24BPP_888;  in fimd_win_set_pixfmt()
514 		val |= WINCONx_WSWP;  in fimd_win_set_pixfmt()
515 		val |= WINCONx_BURSTLEN_16WORD;  in fimd_win_set_pixfmt()
518 		val |= WINCON1_BPPMODE_25BPP_A1888  in fimd_win_set_pixfmt()
520 		val |= WINCONx_WSWP;  in fimd_win_set_pixfmt()
521 		val |= WINCONx_BURSTLEN_16WORD;  in fimd_win_set_pixfmt()
526 		val |= WINCON0_BPPMODE_24BPP_888;  in fimd_win_set_pixfmt()
527 		val |= WINCONx_WSWP;  in fimd_win_set_pixfmt()
528 		val |= WINCONx_BURSTLEN_16WORD;  in fimd_win_set_pixfmt()
543 		val &= ~WINCONx_BURSTLEN_MASK;  in fimd_win_set_pixfmt()
544 		val |= WINCONx_BURSTLEN_4WORD;  in fimd_win_set_pixfmt()
547 	writel(val, ctx->regs + WINCON(win));  in fimd_win_set_pixfmt()
552 		val = VIDISD14C_ALPHA0_R(0xf) |  in fimd_win_set_pixfmt()
559 		writel(val, ctx->regs + VIDOSD_C(win));  in fimd_win_set_pixfmt()
561 		val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |  in fimd_win_set_pixfmt()
563 		writel(val, ctx->regs + VIDWnALPHA0(win));  in fimd_win_set_pixfmt()
564 		writel(val, ctx->regs + VIDWnALPHA1(win));  in fimd_win_set_pixfmt()
590 	u32 reg, bits, val;  in fimd_shadow_protect_win()  local
610 	val = readl(ctx->regs + reg);  in fimd_shadow_protect_win()
612 		val |= bits;  in fimd_shadow_protect_win()
614 		val &= ~bits;  in fimd_shadow_protect_win()
615 	writel(val, ctx->regs + reg);  in fimd_shadow_protect_win()
646 	unsigned long val, size, offset;  in fimd_update_plane()  local
660 	val = (unsigned long)dma_addr;  in fimd_update_plane()
661 	writel(val, ctx->regs + VIDWx_BUF_START(win, 0));  in fimd_update_plane()
665 	val = (unsigned long)(dma_addr + size);  in fimd_update_plane()
666 	writel(val, ctx->regs + VIDWx_BUF_END(win, 0));  in fimd_update_plane()
669 			(unsigned long)dma_addr, val, size);  in fimd_update_plane()
676 	val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |  in fimd_update_plane()
680 	writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));  in fimd_update_plane()
683 	val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) |  in fimd_update_plane()
687 	writel(val, ctx->regs + VIDOSD_A(win));  in fimd_update_plane()
696 	val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |  in fimd_update_plane()
699 	writel(val, ctx->regs + VIDOSD_B(win));  in fimd_update_plane()
709 		val = plane->crtc_w * plane->crtc_h;  in fimd_update_plane()
710 		writel(val, ctx->regs + offset);  in fimd_update_plane()
712 		DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);  in fimd_update_plane()
863 	u32 val;  in fimd_dp_clock_enable()  local
873 	val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;  in fimd_dp_clock_enable()
874 	writel(val, ctx->regs + DP_MIE_CLKCON);  in fimd_dp_clock_enable()
895 	u32 val, clear_bit, start, start_s;  in fimd_irq_handler()  local
898 	val = readl(ctx->regs + VIDINTCON1);  in fimd_irq_handler()
901 	if (val & clear_bit)  in fimd_irq_handler()
1024 		u32 val;  in fimd_probe()  local
1038 		if (of_property_read_u32(i80_if_timings, "cs-setup", &val))  in fimd_probe()
1039 			val = 0;  in fimd_probe()
1040 		ctx->i80ifcon = LCD_CS_SETUP(val);  in fimd_probe()
1041 		if (of_property_read_u32(i80_if_timings, "wr-setup", &val))  in fimd_probe()
1042 			val = 0;  in fimd_probe()
1043 		ctx->i80ifcon |= LCD_WR_SETUP(val);  in fimd_probe()
1044 		if (of_property_read_u32(i80_if_timings, "wr-active", &val))  in fimd_probe()
1045 			val = 1;  in fimd_probe()
1046 		ctx->i80ifcon |= LCD_WR_ACTIVE(val);  in fimd_probe()
1047 		if (of_property_read_u32(i80_if_timings, "wr-hold", &val))  in fimd_probe()
1048 			val = 0;  in fimd_probe()
1049 		ctx->i80ifcon |= LCD_WR_HOLD(val);  in fimd_probe()