Lines Matching refs:reg_values
258 unsigned int *reg_values; member
393 static unsigned int reg_values[] = { variable
438 .reg_values = reg_values,
450 .reg_values = reg_values,
461 .reg_values = reg_values,
471 .reg_values = reg_values,
482 .reg_values = exynos5433_reg_values,
521 DSI_WRITE(dsi, DSIM_SWRST_REG, driver_data->reg_values[RESET_TYPE]); in exynos_dsi_reset()
601 writel(driver_data->reg_values[PLL_TIMER], in exynos_dsi_set_pll()
680 unsigned int *reg_values = driver_data->reg_values; in exynos_dsi_set_phy_ctrl() local
687 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | in exynos_dsi_set_phy_ctrl()
688 reg_values[PHYCTRL_SLEW_UP]; in exynos_dsi_set_phy_ctrl()
696 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; in exynos_dsi_set_phy_ctrl()
712 reg = reg_values[PHYTIMING_CLK_PREPARE] | in exynos_dsi_set_phy_ctrl()
713 reg_values[PHYTIMING_CLK_ZERO] | in exynos_dsi_set_phy_ctrl()
714 reg_values[PHYTIMING_CLK_POST] | in exynos_dsi_set_phy_ctrl()
715 reg_values[PHYTIMING_CLK_TRAIL]; in exynos_dsi_set_phy_ctrl()
728 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | in exynos_dsi_set_phy_ctrl()
729 reg_values[PHYTIMING_HS_TRAIL]; in exynos_dsi_set_phy_ctrl()
860 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); in exynos_dsi_init_link()
1306 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) in exynos_dsi_init()