Lines Matching refs:dp
27 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable) in exynos_dp_enable_video_mute() argument
32 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
34 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
36 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
38 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
42 void exynos_dp_stop_video(struct exynos_dp_device *dp) in exynos_dp_stop_video() argument
46 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
48 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
51 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable) in exynos_dp_lane_swap() argument
62 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); in exynos_dp_lane_swap()
65 void exynos_dp_init_analog_param(struct exynos_dp_device *dp) in exynos_dp_init_analog_param() argument
70 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); in exynos_dp_init_analog_param()
73 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); in exynos_dp_init_analog_param()
76 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); in exynos_dp_init_analog_param()
80 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); in exynos_dp_init_analog_param()
84 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL); in exynos_dp_init_analog_param()
87 void exynos_dp_init_interrupt(struct exynos_dp_device *dp) in exynos_dp_init_interrupt() argument
90 writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL); in exynos_dp_init_interrupt()
93 writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); in exynos_dp_init_interrupt()
94 writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2); in exynos_dp_init_interrupt()
95 writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3); in exynos_dp_init_interrupt()
96 writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); in exynos_dp_init_interrupt()
97 writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_init_interrupt()
100 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); in exynos_dp_init_interrupt()
101 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); in exynos_dp_init_interrupt()
102 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); in exynos_dp_init_interrupt()
103 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); in exynos_dp_init_interrupt()
104 writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK); in exynos_dp_init_interrupt()
107 void exynos_dp_reset(struct exynos_dp_device *dp) in exynos_dp_reset() argument
111 exynos_dp_stop_video(dp); in exynos_dp_reset()
112 exynos_dp_enable_video_mute(dp, 0); in exynos_dp_reset()
117 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_reset()
122 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_reset()
126 exynos_dp_lane_swap(dp, 0); in exynos_dp_reset()
128 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_reset()
129 writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_reset()
130 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_reset()
131 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_reset()
133 writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL); in exynos_dp_reset()
134 writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL); in exynos_dp_reset()
136 writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L); in exynos_dp_reset()
137 writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H); in exynos_dp_reset()
139 writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL); in exynos_dp_reset()
141 writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST); in exynos_dp_reset()
143 writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD); in exynos_dp_reset()
144 writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN); in exynos_dp_reset()
146 writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH); in exynos_dp_reset()
147 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH); in exynos_dp_reset()
149 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_reset()
152 void exynos_dp_swreset(struct exynos_dp_device *dp) in exynos_dp_swreset() argument
154 writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET); in exynos_dp_swreset()
157 void exynos_dp_config_interrupt(struct exynos_dp_device *dp) in exynos_dp_config_interrupt() argument
163 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); in exynos_dp_config_interrupt()
166 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); in exynos_dp_config_interrupt()
169 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); in exynos_dp_config_interrupt()
172 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); in exynos_dp_config_interrupt()
175 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK); in exynos_dp_config_interrupt()
178 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp) in exynos_dp_get_pll_lock_status() argument
182 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); in exynos_dp_get_pll_lock_status()
189 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable) in exynos_dp_set_pll_power_down() argument
194 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
196 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
198 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
200 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); in exynos_dp_set_pll_power_down()
204 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp, in exynos_dp_set_analog_power_down() argument
213 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
215 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
217 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
219 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
224 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
226 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
228 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
230 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
235 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
237 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
239 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
241 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
246 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
248 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
250 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
252 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
257 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
259 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
261 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
263 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
268 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
270 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
272 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
274 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
281 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
283 writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD); in exynos_dp_set_analog_power_down()
291 void exynos_dp_init_analog_func(struct exynos_dp_device *dp) in exynos_dp_init_analog_func() argument
296 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0); in exynos_dp_init_analog_func()
299 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); in exynos_dp_init_analog_func()
301 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL); in exynos_dp_init_analog_func()
303 writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL); in exynos_dp_init_analog_func()
306 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { in exynos_dp_init_analog_func()
307 exynos_dp_set_pll_power_down(dp, 0); in exynos_dp_init_analog_func()
309 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { in exynos_dp_init_analog_func()
312 dev_err(dp->dev, "failed to get pll lock status\n"); in exynos_dp_init_analog_func()
320 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_analog_func()
323 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_analog_func()
326 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp) in exynos_dp_clear_hotplug_interrupts() argument
330 if (gpio_is_valid(dp->hpd_gpio)) in exynos_dp_clear_hotplug_interrupts()
334 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); in exynos_dp_clear_hotplug_interrupts()
337 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_clear_hotplug_interrupts()
340 void exynos_dp_init_hpd(struct exynos_dp_device *dp) in exynos_dp_init_hpd() argument
344 if (gpio_is_valid(dp->hpd_gpio)) in exynos_dp_init_hpd()
347 exynos_dp_clear_hotplug_interrupts(dp); in exynos_dp_init_hpd()
349 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_init_hpd()
351 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_init_hpd()
354 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp) in exynos_dp_get_irq_type() argument
358 if (gpio_is_valid(dp->hpd_gpio)) { in exynos_dp_get_irq_type()
359 reg = gpio_get_value(dp->hpd_gpio); in exynos_dp_get_irq_type()
366 reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); in exynos_dp_get_irq_type()
381 void exynos_dp_reset_aux(struct exynos_dp_device *dp) in exynos_dp_reset_aux() argument
386 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_reset_aux()
388 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_reset_aux()
391 void exynos_dp_init_aux(struct exynos_dp_device *dp) in exynos_dp_init_aux() argument
397 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_init_aux()
399 exynos_dp_reset_aux(dp); in exynos_dp_init_aux()
404 writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL); in exynos_dp_init_aux()
408 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL); in exynos_dp_init_aux()
411 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_aux()
413 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); in exynos_dp_init_aux()
416 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp) in exynos_dp_get_plug_in_status() argument
420 if (gpio_is_valid(dp->hpd_gpio)) { in exynos_dp_get_plug_in_status()
421 if (gpio_get_value(dp->hpd_gpio)) in exynos_dp_get_plug_in_status()
424 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_get_plug_in_status()
432 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp) in exynos_dp_enable_sw_function() argument
436 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_enable_sw_function()
438 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_enable_sw_function()
441 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp) in exynos_dp_start_aux_transaction() argument
448 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_start_aux_transaction()
450 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_start_aux_transaction()
453 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
457 dev_err(dp->dev, "AUX CH command reply failed!\n"); in exynos_dp_start_aux_transaction()
460 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
465 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
468 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
470 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA); in exynos_dp_start_aux_transaction()
475 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA); in exynos_dp_start_aux_transaction()
477 dev_err(dp->dev, "AUX CH error happens: %d\n\n", in exynos_dp_start_aux_transaction()
485 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp, in exynos_dp_write_byte_to_dpcd() argument
496 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_write_byte_to_dpcd()
500 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_write_byte_to_dpcd()
502 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_write_byte_to_dpcd()
504 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_write_byte_to_dpcd()
508 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0); in exynos_dp_write_byte_to_dpcd()
516 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_write_byte_to_dpcd()
519 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_write_byte_to_dpcd()
523 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", in exynos_dp_write_byte_to_dpcd()
530 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp, in exynos_dp_read_byte_from_dpcd() argument
541 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_byte_from_dpcd()
545 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_read_byte_from_dpcd()
547 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_read_byte_from_dpcd()
549 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_read_byte_from_dpcd()
557 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_read_byte_from_dpcd()
560 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_read_byte_from_dpcd()
564 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", in exynos_dp_read_byte_from_dpcd()
569 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0); in exynos_dp_read_byte_from_dpcd()
575 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp, in exynos_dp_write_bytes_to_dpcd() argument
589 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_write_bytes_to_dpcd()
602 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_write_bytes_to_dpcd()
604 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_write_bytes_to_dpcd()
606 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_write_bytes_to_dpcd()
611 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0 in exynos_dp_write_bytes_to_dpcd()
622 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_write_bytes_to_dpcd()
625 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_write_bytes_to_dpcd()
629 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", in exynos_dp_write_bytes_to_dpcd()
639 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp, in exynos_dp_read_bytes_from_dpcd() argument
653 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_bytes_from_dpcd()
667 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_read_bytes_from_dpcd()
669 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_read_bytes_from_dpcd()
671 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_read_bytes_from_dpcd()
680 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_read_bytes_from_dpcd()
683 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_read_bytes_from_dpcd()
687 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", in exynos_dp_read_bytes_from_dpcd()
693 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 in exynos_dp_read_bytes_from_dpcd()
705 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp, in exynos_dp_select_i2c_device() argument
714 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); in exynos_dp_select_i2c_device()
715 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); in exynos_dp_select_i2c_device()
716 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); in exynos_dp_select_i2c_device()
719 writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0); in exynos_dp_select_i2c_device()
728 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_select_i2c_device()
731 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_select_i2c_device()
733 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); in exynos_dp_select_i2c_device()
738 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp, in exynos_dp_read_byte_from_i2c() argument
750 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_byte_from_i2c()
753 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr); in exynos_dp_read_byte_from_i2c()
764 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); in exynos_dp_read_byte_from_i2c()
767 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_read_byte_from_i2c()
771 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", in exynos_dp_read_byte_from_i2c()
777 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0); in exynos_dp_read_byte_from_i2c()
782 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp, in exynos_dp_read_bytes_from_i2c() argument
798 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); in exynos_dp_read_bytes_from_i2c()
801 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_read_bytes_from_i2c()
803 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); in exynos_dp_read_bytes_from_i2c()
810 retval = exynos_dp_select_i2c_device(dp, in exynos_dp_read_bytes_from_i2c()
824 writel(reg, dp->reg_base + in exynos_dp_read_bytes_from_i2c()
828 retval = exynos_dp_start_aux_transaction(dp); in exynos_dp_read_bytes_from_i2c()
832 dev_dbg(dp->dev, in exynos_dp_read_bytes_from_i2c()
837 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM); in exynos_dp_read_bytes_from_i2c()
840 dev_err(dp->dev, "Defer: %d\n\n", reg); in exynos_dp_read_bytes_from_i2c()
846 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0 in exynos_dp_read_bytes_from_i2c()
855 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype) in exynos_dp_set_link_bandwidth() argument
861 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET); in exynos_dp_set_link_bandwidth()
864 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype) in exynos_dp_get_link_bandwidth() argument
868 reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET); in exynos_dp_get_link_bandwidth()
872 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count) in exynos_dp_set_lane_count() argument
877 writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); in exynos_dp_set_lane_count()
880 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count) in exynos_dp_get_lane_count() argument
884 reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); in exynos_dp_get_lane_count()
888 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable) in exynos_dp_enable_enhanced_mode() argument
893 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
895 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
897 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
899 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_enable_enhanced_mode()
903 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp, in exynos_dp_set_training_pattern() argument
911 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
915 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
919 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
923 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
929 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_set_training_pattern()
936 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level) in exynos_dp_set_lane0_pre_emphasis() argument
940 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_pre_emphasis()
943 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_pre_emphasis()
946 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level) in exynos_dp_set_lane1_pre_emphasis() argument
950 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_pre_emphasis()
953 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_pre_emphasis()
956 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level) in exynos_dp_set_lane2_pre_emphasis() argument
960 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_set_lane2_pre_emphasis()
963 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_set_lane2_pre_emphasis()
966 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level) in exynos_dp_set_lane3_pre_emphasis() argument
970 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_set_lane3_pre_emphasis()
973 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_set_lane3_pre_emphasis()
976 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp, in exynos_dp_set_lane0_link_training() argument
982 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_set_lane0_link_training()
985 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp, in exynos_dp_set_lane1_link_training() argument
991 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_set_lane1_link_training()
994 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp, in exynos_dp_set_lane2_link_training() argument
1000 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_set_lane2_link_training()
1003 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp, in exynos_dp_set_lane3_link_training() argument
1009 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_set_lane3_link_training()
1012 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp) in exynos_dp_get_lane0_link_training() argument
1016 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); in exynos_dp_get_lane0_link_training()
1020 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp) in exynos_dp_get_lane1_link_training() argument
1024 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); in exynos_dp_get_lane1_link_training()
1028 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp) in exynos_dp_get_lane2_link_training() argument
1032 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); in exynos_dp_get_lane2_link_training()
1036 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp) in exynos_dp_get_lane3_link_training() argument
1040 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); in exynos_dp_get_lane3_link_training()
1044 void exynos_dp_reset_macro(struct exynos_dp_device *dp) in exynos_dp_reset_macro() argument
1048 reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST); in exynos_dp_reset_macro()
1050 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); in exynos_dp_reset_macro()
1056 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); in exynos_dp_reset_macro()
1059 void exynos_dp_init_video(struct exynos_dp_device *dp) in exynos_dp_init_video() argument
1064 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); in exynos_dp_init_video()
1067 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_init_video()
1070 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_init_video()
1073 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_init_video()
1076 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8); in exynos_dp_init_video()
1079 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp) in exynos_dp_set_video_color_format() argument
1084 reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) | in exynos_dp_set_video_color_format()
1085 (dp->video_info->color_depth << IN_BPC_SHIFT) | in exynos_dp_set_video_color_format()
1086 (dp->video_info->color_space << IN_COLOR_F_SHIFT); in exynos_dp_set_video_color_format()
1087 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2); in exynos_dp_set_video_color_format()
1090 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); in exynos_dp_set_video_color_format()
1092 if (dp->video_info->ycbcr_coeff) in exynos_dp_set_video_color_format()
1096 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); in exynos_dp_set_video_color_format()
1099 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp) in exynos_dp_is_slave_video_stream_clock_on() argument
1103 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()
1104 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()
1106 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1); in exynos_dp_is_slave_video_stream_clock_on()
1109 dev_dbg(dp->dev, "Input stream clock not detected.\n"); in exynos_dp_is_slave_video_stream_clock_on()
1113 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()
1114 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()
1116 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2); in exynos_dp_is_slave_video_stream_clock_on()
1117 dev_dbg(dp->dev, "wait SYS_CTL_2.\n"); in exynos_dp_is_slave_video_stream_clock_on()
1120 dev_dbg(dp->dev, "Input stream clk is changing\n"); in exynos_dp_is_slave_video_stream_clock_on()
1127 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp, in exynos_dp_set_video_cr_mn() argument
1135 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1137 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1139 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0); in exynos_dp_set_video_cr_mn()
1141 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1); in exynos_dp_set_video_cr_mn()
1143 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2); in exynos_dp_set_video_cr_mn()
1146 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0); in exynos_dp_set_video_cr_mn()
1148 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1); in exynos_dp_set_video_cr_mn()
1150 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2); in exynos_dp_set_video_cr_mn()
1152 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1154 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); in exynos_dp_set_video_cr_mn()
1156 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0); in exynos_dp_set_video_cr_mn()
1157 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1); in exynos_dp_set_video_cr_mn()
1158 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2); in exynos_dp_set_video_cr_mn()
1162 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type) in exynos_dp_set_video_timing_mode() argument
1167 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1169 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1171 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1173 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_set_video_timing_mode()
1177 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable) in exynos_dp_enable_video_master() argument
1182 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1185 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1187 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1190 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_enable_video_master()
1194 void exynos_dp_start_video(struct exynos_dp_device *dp) in exynos_dp_start_video() argument
1198 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_start_video()
1200 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_start_video()
1203 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp) in exynos_dp_is_video_stream_on() argument
1207 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_is_video_stream_on()
1208 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_is_video_stream_on()
1210 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3); in exynos_dp_is_video_stream_on()
1212 dev_dbg(dp->dev, "Input video stream is not detected.\n"); in exynos_dp_is_video_stream_on()
1219 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp) in exynos_dp_config_video_slave_mode() argument
1223 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_config_video_slave_mode()
1226 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); in exynos_dp_config_video_slave_mode()
1228 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1230 reg |= (dp->video_info->interlaced << 2); in exynos_dp_config_video_slave_mode()
1231 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1233 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1235 reg |= (dp->video_info->v_sync_polarity << 1); in exynos_dp_config_video_slave_mode()
1236 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1238 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1240 reg |= (dp->video_info->h_sync_polarity << 0); in exynos_dp_config_video_slave_mode()
1241 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); in exynos_dp_config_video_slave_mode()
1244 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); in exynos_dp_config_video_slave_mode()
1247 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp) in exynos_dp_enable_scrambling() argument
1251 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_enable_scrambling()
1253 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_enable_scrambling()
1256 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp) in exynos_dp_disable_scrambling() argument
1260 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_disable_scrambling()
1262 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); in exynos_dp_disable_scrambling()