Lines Matching refs:ctx
74 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, in decon_set_bits() argument
77 val = (val & mask) | (readl(ctx->addr + reg) & ~mask); in decon_set_bits()
78 writel(val, ctx->addr + reg); in decon_set_bits()
83 struct decon_context *ctx = crtc->ctx; in decon_enable_vblank() local
86 if (test_bit(BIT_SUSPENDED, &ctx->flags)) in decon_enable_vblank()
89 if (test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) { in decon_enable_vblank()
91 if (ctx->out_type == IFTYPE_I80) in decon_enable_vblank()
96 writel(val, ctx->addr + DECON_VIDINTCON0); in decon_enable_vblank()
104 struct decon_context *ctx = crtc->ctx; in decon_disable_vblank() local
106 if (test_bit(BIT_SUSPENDED, &ctx->flags)) in decon_disable_vblank()
109 if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags)) in decon_disable_vblank()
110 writel(0, ctx->addr + DECON_VIDINTCON0); in decon_disable_vblank()
113 static void decon_setup_trigger(struct decon_context *ctx) in decon_setup_trigger() argument
115 u32 val = (ctx->out_type != IFTYPE_HDMI) in decon_setup_trigger()
120 writel(val, ctx->addr + DECON_TRIGCON); in decon_setup_trigger()
125 struct decon_context *ctx = crtc->ctx; in decon_commit() local
129 if (test_bit(BIT_SUSPENDED, &ctx->flags)) in decon_commit()
132 if (ctx->out_type == IFTYPE_HDMI) { in decon_commit()
139 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0); in decon_commit()
143 writel(val, ctx->addr + DECON_CMU); in decon_commit()
147 if (ctx->out_type == IFTYPE_I80) in decon_commit()
151 writel(val, ctx->addr + DECON_VIDOUTCON0); in decon_commit()
155 writel(val, ctx->addr + DECON_VIDTCON2); in decon_commit()
157 if (ctx->out_type != IFTYPE_I80) { in decon_commit()
162 writel(val, ctx->addr + DECON_VIDTCON00); in decon_commit()
166 writel(val, ctx->addr + DECON_VIDTCON01); in decon_commit()
172 writel(val, ctx->addr + DECON_VIDTCON10); in decon_commit()
176 writel(val, ctx->addr + DECON_VIDTCON11); in decon_commit()
179 decon_setup_trigger(ctx); in decon_commit()
182 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); in decon_commit()
185 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, in decon_win_set_pixfmt() argument
190 val = readl(ctx->addr + DECON_WINCONx(win)); in decon_win_set_pixfmt()
234 writel(val, ctx->addr + DECON_WINCONx(win)); in decon_win_set_pixfmt()
237 static void decon_shadow_protect_win(struct decon_context *ctx, int win, in decon_shadow_protect_win() argument
240 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win), in decon_shadow_protect_win()
247 struct decon_context *ctx = crtc->ctx; in decon_atomic_begin() local
249 if (test_bit(BIT_SUSPENDED, &ctx->flags)) in decon_atomic_begin()
252 decon_shadow_protect_win(ctx, plane->zpos, true); in decon_atomic_begin()
262 struct decon_context *ctx = crtc->ctx; in decon_update_plane() local
269 if (test_bit(BIT_SUSPENDED, &ctx->flags)) in decon_update_plane()
273 writel(val, ctx->addr + DECON_VIDOSDxA(win)); in decon_update_plane()
277 writel(val, ctx->addr + DECON_VIDOSDxB(win)); in decon_update_plane()
281 writel(val, ctx->addr + DECON_VIDOSDxC(win)); in decon_update_plane()
285 writel(val, ctx->addr + DECON_VIDOSDxD(win)); in decon_update_plane()
287 writel(plane->dma_addr[0], ctx->addr + DECON_VIDW0xADD0B0(win)); in decon_update_plane()
290 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); in decon_update_plane()
292 if (ctx->out_type != IFTYPE_HDMI) in decon_update_plane()
298 writel(val, ctx->addr + DECON_VIDW0xADD2(win)); in decon_update_plane()
300 decon_win_set_pixfmt(ctx, win, state->fb); in decon_update_plane()
303 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); in decon_update_plane()
306 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); in decon_update_plane()
312 struct decon_context *ctx = crtc->ctx; in decon_disable_plane() local
315 if (test_bit(BIT_SUSPENDED, &ctx->flags)) in decon_disable_plane()
318 decon_shadow_protect_win(ctx, win, true); in decon_disable_plane()
321 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); in decon_disable_plane()
323 decon_shadow_protect_win(ctx, win, false); in decon_disable_plane()
326 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); in decon_disable_plane()
332 struct decon_context *ctx = crtc->ctx; in decon_atomic_flush() local
334 if (test_bit(BIT_SUSPENDED, &ctx->flags)) in decon_atomic_flush()
337 decon_shadow_protect_win(ctx, plane->zpos, false); in decon_atomic_flush()
339 if (ctx->out_type == IFTYPE_I80) in decon_atomic_flush()
340 set_bit(BIT_WIN_UPDATED, &ctx->flags); in decon_atomic_flush()
343 static void decon_swreset(struct decon_context *ctx) in decon_swreset() argument
347 writel(0, ctx->addr + DECON_VIDCON0); in decon_swreset()
349 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS) in decon_swreset()
356 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); in decon_swreset()
358 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET) in decon_swreset()
365 if (ctx->out_type != IFTYPE_HDMI) in decon_swreset()
368 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); in decon_swreset()
369 decon_set_bits(ctx, DECON_CMU, in decon_swreset()
371 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); in decon_swreset()
373 ctx->addr + DECON_CRCCTRL); in decon_swreset()
374 decon_setup_trigger(ctx); in decon_swreset()
379 struct decon_context *ctx = crtc->ctx; in decon_enable() local
383 if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags)) in decon_enable()
386 pm_runtime_get_sync(ctx->dev); in decon_enable()
389 ret = clk_prepare_enable(ctx->clks[i]); in decon_enable()
394 set_bit(BIT_CLKS_ENABLED, &ctx->flags); in decon_enable()
397 if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags)) in decon_enable()
398 decon_enable_vblank(ctx->crtc); in decon_enable()
400 decon_commit(ctx->crtc); in decon_enable()
405 clk_disable_unprepare(ctx->clks[i]); in decon_enable()
407 set_bit(BIT_SUSPENDED, &ctx->flags); in decon_enable()
412 struct decon_context *ctx = crtc->ctx; in decon_disable() local
415 if (test_bit(BIT_SUSPENDED, &ctx->flags)) in decon_disable()
423 for (i = ctx->first_win; i < WINDOWS_NR; i++) in decon_disable()
424 decon_disable_plane(crtc, &ctx->planes[i]); in decon_disable()
426 decon_swreset(ctx); in decon_disable()
429 clk_disable_unprepare(ctx->clks[i]); in decon_disable()
431 clear_bit(BIT_CLKS_ENABLED, &ctx->flags); in decon_disable()
433 pm_runtime_put_sync(ctx->dev); in decon_disable()
435 set_bit(BIT_SUSPENDED, &ctx->flags); in decon_disable()
440 struct decon_context *ctx = crtc->ctx; in decon_te_irq_handler() local
442 if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags)) in decon_te_irq_handler()
445 if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags)) in decon_te_irq_handler()
446 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); in decon_te_irq_handler()
448 drm_crtc_handle_vblank(&ctx->crtc->base); in decon_te_irq_handler()
453 struct decon_context *ctx = crtc->ctx; in decon_clear_channels() local
459 ret = clk_prepare_enable(ctx->clks[i]); in decon_clear_channels()
465 decon_shadow_protect_win(ctx, win, true); in decon_clear_channels()
466 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); in decon_clear_channels()
467 decon_shadow_protect_win(ctx, win, false); in decon_clear_channels()
468 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); in decon_clear_channels()
475 clk_disable_unprepare(ctx->clks[i]); in decon_clear_channels()
493 struct decon_context *ctx = dev_get_drvdata(dev); in decon_bind() local
502 ctx->drm_dev = drm_dev; in decon_bind()
503 ctx->pipe = priv->pipe++; in decon_bind()
505 for (win = ctx->first_win; win < WINDOWS_NR; win++) { in decon_bind()
506 int tmp = (win == ctx->first_win) ? 0 : win; in decon_bind()
509 ret = exynos_plane_init(drm_dev, &ctx->planes[win], in decon_bind()
510 1 << ctx->pipe, type, decon_formats, in decon_bind()
516 exynos_plane = &ctx->planes[ctx->first_win]; in decon_bind()
517 out_type = (ctx->out_type == IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI in decon_bind()
519 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, in decon_bind()
520 ctx->pipe, out_type, in decon_bind()
521 &decon_crtc_ops, ctx); in decon_bind()
522 if (IS_ERR(ctx->crtc)) { in decon_bind()
523 ret = PTR_ERR(ctx->crtc); in decon_bind()
527 decon_clear_channels(ctx->crtc); in decon_bind()
541 struct decon_context *ctx = dev_get_drvdata(dev); in decon_unbind() local
543 decon_disable(ctx->crtc); in decon_unbind()
546 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); in decon_unbind()
556 struct decon_context *ctx = dev_id; in decon_irq_handler() local
560 if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags)) in decon_irq_handler()
563 val = readl(ctx->addr + DECON_VIDINTCON1); in decon_irq_handler()
567 for (win = ctx->first_win; win < WINDOWS_NR ; win++) { in decon_irq_handler()
568 struct exynos_drm_plane *plane = &ctx->planes[win]; in decon_irq_handler()
573 exynos_drm_crtc_finish_update(ctx->crtc, plane); in decon_irq_handler()
577 writel(val, ctx->addr + DECON_VIDINTCON1); in decon_irq_handler()
601 struct decon_context *ctx; in exynos5433_decon_probe() local
606 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); in exynos5433_decon_probe()
607 if (!ctx) in exynos5433_decon_probe()
610 __set_bit(BIT_SUSPENDED, &ctx->flags); in exynos5433_decon_probe()
611 ctx->dev = dev; in exynos5433_decon_probe()
614 ctx->out_type = (enum decon_iftype)of_id->data; in exynos5433_decon_probe()
616 if (ctx->out_type == IFTYPE_HDMI) in exynos5433_decon_probe()
617 ctx->first_win = 1; in exynos5433_decon_probe()
619 ctx->out_type = IFTYPE_I80; in exynos5433_decon_probe()
624 clk = devm_clk_get(ctx->dev, decon_clks_name[i]); in exynos5433_decon_probe()
628 ctx->clks[i] = clk; in exynos5433_decon_probe()
637 ctx->addr = devm_ioremap_resource(dev, res); in exynos5433_decon_probe()
638 if (IS_ERR(ctx->addr)) { in exynos5433_decon_probe()
640 return PTR_ERR(ctx->addr); in exynos5433_decon_probe()
644 (ctx->out_type == IFTYPE_I80) ? "lcd_sys" : "vsync"); in exynos5433_decon_probe()
651 "drm_decon", ctx); in exynos5433_decon_probe()
657 platform_set_drvdata(pdev, ctx); in exynos5433_decon_probe()