110 	u8 tmp;  in cirrus_set_start_address()  local
117 	tmp = RREG8(CRT_DATA);  in cirrus_set_start_address()
118 	tmp &= 0xf2;  in cirrus_set_start_address()
119 	tmp |= (addr >> 16) & 0x01;  in cirrus_set_start_address()
120 	tmp |= (addr >> 15) & 0x0c;  in cirrus_set_start_address()
121 	WREG_CRT(0x1b, tmp);  in cirrus_set_start_address()
123 	tmp = RREG8(CRT_DATA);  in cirrus_set_start_address()
124 	tmp &= 0x7f;  in cirrus_set_start_address()
125 	tmp |= (addr >> 12) & 0x80;  in cirrus_set_start_address()
126 	WREG_CRT(0x1d, tmp);  in cirrus_set_start_address()
202 	int tmp;  in cirrus_crtc_mode_set()  local
229 	tmp = 0x40;  in cirrus_crtc_mode_set()
231 		tmp |= 0x20;  in cirrus_crtc_mode_set()
232 	WREG_CRT(VGA_CRTC_MAX_SCAN, tmp);  in cirrus_crtc_mode_set()
237 	tmp = 16;  in cirrus_crtc_mode_set()
239 		tmp |= 1;  in cirrus_crtc_mode_set()
241 		tmp |= 2;  in cirrus_crtc_mode_set()
243 		tmp |= 8;  in cirrus_crtc_mode_set()
245 		tmp |= 32;  in cirrus_crtc_mode_set()
247 		tmp |= 64;  in cirrus_crtc_mode_set()
248 	WREG_CRT(VGA_CRTC_OVERFLOW, tmp);  in cirrus_crtc_mode_set()
250 	tmp = 0;  in cirrus_crtc_mode_set()
255 		tmp |= 16;  in cirrus_crtc_mode_set()
257 		tmp |= 32;  in cirrus_crtc_mode_set()
259 		tmp |= 64;  in cirrus_crtc_mode_set()
261 		tmp |= 128;  in cirrus_crtc_mode_set()
263 	WREG_CRT(CL_CRT1A, tmp);  in cirrus_crtc_mode_set()
295 	tmp = crtc->primary->fb->pitches[0] / 8;  in cirrus_crtc_mode_set()
296 	WREG_CRT(VGA_CRTC_OFFSET, tmp);  in cirrus_crtc_mode_set()
299 	tmp = 0x22;  in cirrus_crtc_mode_set()
300 	tmp |= (crtc->primary->fb->pitches[0] >> 7) & 0x10;  in cirrus_crtc_mode_set()
301 	tmp |= (crtc->primary->fb->pitches[0] >> 6) & 0x40;  in cirrus_crtc_mode_set()
302 	WREG_CRT(0x1b, tmp);  in cirrus_crtc_mode_set()