Lines Matching refs:WREG_CRT
113 WREG_CRT(0x0c, (u8)((addr >> 8) & 0xff)); in cirrus_set_start_address()
114 WREG_CRT(0x0d, (u8)(addr & 0xff)); in cirrus_set_start_address()
121 WREG_CRT(0x1b, tmp); in cirrus_set_start_address()
126 WREG_CRT(0x1d, tmp); in cirrus_set_start_address()
221 WREG_CRT(VGA_CRTC_V_SYNC_END, 0x20); in cirrus_crtc_mode_set()
222 WREG_CRT(VGA_CRTC_H_TOTAL, htotal); in cirrus_crtc_mode_set()
223 WREG_CRT(VGA_CRTC_H_DISP, hdispend); in cirrus_crtc_mode_set()
224 WREG_CRT(VGA_CRTC_H_SYNC_START, hsyncstart); in cirrus_crtc_mode_set()
225 WREG_CRT(VGA_CRTC_H_SYNC_END, hsyncend); in cirrus_crtc_mode_set()
226 WREG_CRT(VGA_CRTC_V_TOTAL, vtotal & 0xff); in cirrus_crtc_mode_set()
227 WREG_CRT(VGA_CRTC_V_DISP_END, vdispend & 0xff); in cirrus_crtc_mode_set()
232 WREG_CRT(VGA_CRTC_MAX_SCAN, tmp); in cirrus_crtc_mode_set()
248 WREG_CRT(VGA_CRTC_OVERFLOW, tmp); in cirrus_crtc_mode_set()
263 WREG_CRT(CL_CRT1A, tmp); in cirrus_crtc_mode_set()
266 WREG_CRT(VGA_CRTC_MODE, 0x03); in cirrus_crtc_mode_set()
296 WREG_CRT(VGA_CRTC_OFFSET, tmp); in cirrus_crtc_mode_set()
302 WREG_CRT(0x1b, tmp); in cirrus_crtc_mode_set()