144 	writeb_relaxed(val, ptr);  in dw_hdmi_writel()
145 	writeb_relaxed(val >> 8, ptr + 1);  in dw_hdmi_writel()
146 	writeb_relaxed(val >> 16, ptr + 2);  in dw_hdmi_writel()
147 	writeb_relaxed(val >> 24, ptr + 3);  in dw_hdmi_writel()
250 	writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL,  in dw_hdmi_start_dma()
260 	writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, base + HDMI_AHB_DMA_MASK);  in dw_hdmi_start_dma()
272 	writeb_relaxed(~0, dw->data.base + HDMI_AHB_DMA_MASK);  in dw_hdmi_stop_dma()
273 	writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, dw->data.base + HDMI_AHB_DMA_STOP);  in dw_hdmi_stop_dma()
286 	writeb_relaxed(stat, dw->data.base + HDMI_IH_AHBDMAAUD_STAT0);  in snd_dw_hdmi_irq()
355 	writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST,  in dw_hdmi_open()
359 	writeb_relaxed(~0, base + HDMI_AHB_DMA_POL);  in dw_hdmi_open()
360 	writeb_relaxed(~0, base + HDMI_AHB_DMA_BUFFPOL);  in dw_hdmi_open()
363 	writeb_relaxed(~0, base + HDMI_AHB_DMA_MASK);  in dw_hdmi_open()
364 	writeb_relaxed(~0, base + HDMI_IH_AHBDMAAUD_STAT0);  in dw_hdmi_open()
372 	writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL &  in dw_hdmi_open()
384 	writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,  in dw_hdmi_close()
449 	writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD);  in dw_hdmi_prepare()
450 	writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0);  in dw_hdmi_prepare()
451 	writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1);  in dw_hdmi_prepare()
452 	writeb_relaxed(layout, dw->data.base + HDMI_FC_AUDSCONF);  in dw_hdmi_prepare()
453 	writeb_relaxed(ca, dw->data.base + HDMI_FC_AUDICONF2);  in dw_hdmi_prepare()
542 	writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,  in snd_dw_hdmi_probe()