Lines Matching refs:UCHAR
48 #ifndef UCHAR
49 typedef unsigned char UCHAR; typedef
197 UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible
198 UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware
208 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
223 UCHAR ucExtendedFunctionCode;
224 UCHAR ucReserved;
398 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
399 UCHAR ucReserved; //may expand to return larger Fbdiv later
400 UCHAR ucFbDiv; //return value
401 UCHAR ucPostDiv; //return value
407 …UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engi…
409 UCHAR ucPostDiv; //return post div to be written to register
453 UCHAR ucRefDiv; //Output Parameter
454 UCHAR ucPostDiv; //Output Parameter
455 UCHAR ucCntlFlag; //Output Parameter
456 UCHAR ucReserved;
485 UCHAR ucRefDiv; //Output Parameter
486 UCHAR ucPostDiv; //Output Parameter
489 UCHAR ucCntlFlag; //Output Flags
490 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
492 UCHAR ucReserved;
512 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider
513 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider
514 UCHAR ucPllCntlFlag; //Output Flags: control flag
515 UCHAR ucReserved;
533 UCHAR ucDllSpeed; //Output
534 UCHAR ucPostDiv; //Output
536 …UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-Stro…
537 UCHAR ucPllCntlFlag; //Output:
539 UCHAR ucBWCntl;
632 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
633 UCHAR ucPadding[3];
642 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
643 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
644 UCHAR ucPadding[2];
649 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
650 UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT
651 UCHAR ucPadding[2];
660 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
661 UCHAR ucPadding[3];
671 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
672 UCHAR ucMisc; //Valid only when table revision =1.3 and above
690 …UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as …
691 UCHAR ucAction; // 0: turn off encoder
706 UCHAR ucConfig;
714 UCHAR ucAction; // =0: turn off encoder
716 UCHAR ucEncoderMode;
722 UCHAR ucLaneNum; // how many lanes to enable
723 UCHAR ucReserved[2];
766 UCHAR ucReserved1:2;
767 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
768 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
769 UCHAR ucReserved:1;
770 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
772 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
773 UCHAR ucReserved:1;
774 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
775 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
776 UCHAR ucReserved1:2;
785 UCHAR ucAction;
786 UCHAR ucEncoderMode;
792 UCHAR ucLaneNum; // how many lanes to enable
793 …UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used…
794 UCHAR ucReserved;
833 UCHAR ucReserved1:1;
834 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
835 UCHAR ucReserved:3;
836 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
838 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
839 UCHAR ucReserved:3;
840 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
841 UCHAR ucReserved1:1;
860 UCHAR ucAction;
862 UCHAR ucEncoderMode;
869 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
874 UCHAR ucLaneNum; // how many lanes to enable
875 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
876 UCHAR ucReserved;
886 UCHAR ucReserved1:1;
887 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
888 UCHAR ucReserved:2;
889 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
891 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
892 UCHAR ucReserved:2;
893 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
894 UCHAR ucReserved1:1;
917 UCHAR ucConfig;
919 UCHAR ucAction;
921 UCHAR ucEncoderMode;
928 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
933 UCHAR ucLaneNum; // how many lanes to enable
934 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
935 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
958 UCHAR ucLaneSel;
959 UCHAR ucLaneSet;
970 UCHAR ucConfig;
984 UCHAR ucAction; // =0: turn off encoder
986 UCHAR ucReserved[4];
1039 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1042 UCHAR ucReserved:1;
1043 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1044 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/…
1045 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1048 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1049 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1051 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1052 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1053 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1055 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/…
1056 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1057 UCHAR ucReserved:1;
1058 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1099 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1100 UCHAR ucReserved[4];
1106 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1109 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1110 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1111 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1113 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1114 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1116 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1117 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1118 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1120 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1121 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1122 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1138 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1139 UCHAR ucLaneNum;
1140 UCHAR ucReserved[3];
1181 UCHAR ucLaneSel;
1184 UCHAR ucLaneSet;
1187 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1188 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1189 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1191 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1192 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1193 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1202 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1205 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1206 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1207 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1209 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1210 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1212 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1213 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1214 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1216 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1217 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1218 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1235 UCHAR ucConfig;
1237 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1238 UCHAR ucLaneNum;
1239 UCHAR ucReserved[3];
1271 UCHAR ucReservd1:1;
1272 UCHAR ucHPDSel:3;
1273 UCHAR ucPhyClkSrcId:2;
1274 UCHAR ucCoherentMode:1;
1275 UCHAR ucReserved:1;
1277 UCHAR ucReserved:1;
1278 UCHAR ucCoherentMode:1;
1279 UCHAR ucPhyClkSrcId:2;
1280 UCHAR ucHPDSel:3;
1281 UCHAR ucReservd1:1;
1288 …UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIP…
1289 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1290 UCHAR ucLaneNum; // indicate lane number 1-8
1291 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1292 UCHAR ucDigMode; // indicate DIG mode
1295 UCHAR ucConfig;
1297 UCHAR ucDigEncoderSel; // indicate DIG front end encoder
1298 UCHAR ucDPLaneSet;
1299 UCHAR ucReserved;
1300 UCHAR ucReserved1;
1381 …UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE…
1382 UCHAR ucAction; //
1383 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1384 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1385 …UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT …
1386 UCHAR ucReserved;
1424 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
1429 UCHAR aucPadding[3]; // padding to DWORD aligned
1469 UCHAR ucAction;
1470 UCHAR ucBriLevel;
1481 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1482 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1496 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1497 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1498 UCHAR ucPadding[2];
1511 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1512 UCHAR ucPadding[3];
1521 UCHAR ucH_Replication; // horizontal replication
1522 UCHAR ucV_Replication; // vertical replication
1523 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1524 UCHAR ucPadding;
1533 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1534 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1535 UCHAR ucPadding[2];
1541 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1542 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1543 …UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1544 UCHAR ucPadding;
1570 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1571 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1572 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1573 UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR
1588 UCHAR ucPostDiv; // post divider
1589 UCHAR ucFracFbDiv; // fractional feedback divider
1590 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1591 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1592 UCHAR ucCRTC; // Which CRTC uses this Ppll
1593 UCHAR ucPadding;
1608 UCHAR ucPostDiv; // post divider
1609 UCHAR ucFracFbDiv; // fractional feedback divider
1610 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1611 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1612 UCHAR ucCRTC; // Which CRTC uses this Ppll
1613 …UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device i…
1655 UCHAR ucPostDiv; // post divider
1656 UCHAR ucFracFbDiv; // fractional feedback divider
1657 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1658 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
1661 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1662 …UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1664 …UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC …
1675 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
1678 UCHAR ucReserved;
1679 …UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver …
1684 UCHAR ucPostDiv; // post divider.
1685 UCHAR ucRefDiv; // Reference divider
1686 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1687 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1689 UCHAR ucEncoderMode; // Encoder mode:
1690 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1732 UCHAR ucPostDiv; // post divider.
1733 UCHAR ucRefDiv; // Reference divider
1734 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1735 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1737 UCHAR ucEncoderMode; // Encoder mode:
1738 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1770 UCHAR ucStatus;
1771 …UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCI…
1772 UCHAR ucReserved[2];
1787 UCHAR ucTransmitterID;
1788 UCHAR ucEncodeMode;
1791 …UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow …
1792 UCHAR ucConfig; //if none DVO, not defined yet
1794 UCHAR ucReserved[3];
1803 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
1804 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1805 …UCHAR ucDispPllConfig; // display pll configure parameter defined as following DIS…
1806 UCHAR ucExtTransmitterID; // external encoder id.
1807 UCHAR ucReserved[2];
1826 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
1827 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
1828 UCHAR ucReserved[2];
1845 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
1846 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
1847 UCHAR ucPadding[2];
1880 UCHAR ucSlaveAddr; //Read from which slave
1881 UCHAR ucLineNumber; //Read from which HW assisted line
1902 UCHAR ucData; //PS data1
1903 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
1904 UCHAR ucSlaveAddr; //Write to which slave
1905 UCHAR ucLineNumber; //Write from which HW assisted line
1913 UCHAR ucSlaveAddr; //Write to which slave
1914 UCHAR ucLineNumber; //Write from which HW assisted line
1926 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1927 UCHAR ucPwrBehaviorId;
1933 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1934 UCHAR ucReserved;
1948 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int.…
1949 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1950 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1951 UCHAR ucPadding[3];
1958 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int.…
1959 UCHAR ucSpreadSpectrumStep; //
1960 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1961 UCHAR ucSpreadSpectrumDelay;
1962 UCHAR ucSpreadSpectrumRange;
1963 UCHAR ucPadding;
1970 …UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int…
1971 UCHAR ucSpreadSpectrumStep; //
1972 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1973 UCHAR ucSpreadSpectrumDelay;
1974 UCHAR ucSpreadSpectrumRange;
1975 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
1981 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1985 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2006 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2010 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2073 UCHAR ucMisc; // bit0=0: Enable single link
2077 UCHAR ucAction; // 0: turn off encoder
2093 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
2094 UCHAR ucAction; // 0: turn off encoder
2096 UCHAR ucTruncate; // bit0=0: Disable truncate
2100 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2104 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2110 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
2143 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2144 …UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1…
2145 UCHAR ucPadding[2];
2183 UCHAR ucDVOConfig;
2184 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2185 UCHAR ucReseved[4];
2192 UCHAR ucDVOConfig;
2193 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2194 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR
2195 UCHAR ucReseved[3];
2268 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2269 UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
2270 UCHAR ucVoltageIndex; // An index to tell which voltage level
2271 UCHAR ucReserved;
2276 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2277 …UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power …
2284 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2285 UCHAR ucVoltageMode; // Indicate action: Set voltage level
2335 …UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/…
2336 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2374 …UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/…
2375 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2398 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
2399 UCHAR ucAction; // 0: turn off encoder
2473 …UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2…
2474 …UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal…
2475 UCHAR ucVideoPortInfo; // Provides the video port capabilities
2476 UCHAR ucHostPortInfo; // Provides host port configuration information
2487 …UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and vid…
2488 …UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and …
2489 …UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on produ…
2490 …UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM aud…
2491 …UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio…
2492 …UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (…
2493 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2494 …UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical co…
2495 …UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical co…
2496 …UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical co…
2497 …UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical co…
2498 …UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical co…
2591 UCHAR ucASICMaxTemperature;
2592 UCHAR ucPadding[3]; //Don't use them
2607 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2608 UCHAR ucDesign_ID; //Indicate what is the board design
2609 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2625 UCHAR ucASICMaxTemperature;
2626 UCHAR ucMinAllowedBL_Level;
2627 UCHAR ucPadding[2]; //Don't use them
2643 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2644 UCHAR ucDesign_ID; //Indicate what is the board design
2645 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2661 UCHAR ucASICMaxTemperature;
2662 UCHAR ucMinAllowedBL_Level;
2663 UCHAR ucPadding[2]; //Don't use them
2680 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2681 UCHAR ucDesign_ID; //Indicate what is the board design
2682 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2698 UCHAR ucASICMaxTemperature;
2699 UCHAR ucMinAllowedBL_Level;
2718 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2719 UCHAR ucDesign_ID; //Indicate what is the board design
2720 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2737 UCHAR ucReserved1; //Was ucASICMaxTemperature;
2738 UCHAR ucMinAllowedBL_Level;
2758 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2759 UCHAR ucReserved4[3];
2769 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level
2770 UCHAR ucReserved:2; // Bit[3:2] Reserved
2771 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID
2787 UCHAR ucReserved3; //Was ucASICMaxTemperature;
2788 UCHAR ucMinAllowedBL_Level;
2794 UCHAR ucRemoteDisplayConfig;
2795 …UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and us…
2806 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2807 …UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ..…
2809 UCHAR ucReserved9;
2837 UCHAR ucNumberOfCyclesInPeriodHi;
2838 …UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing des…
2852 UCHAR ucMaxNBVoltage;
2853 UCHAR ucMinNBVoltage;
2854 …UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[…
2855 …UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOf…
2856 …UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM…
2857 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
2858 UCHAR ucMaxNBVoltageHigh;
2859 UCHAR ucMinNBVoltageHigh;
2916 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
2917 UCHAR ucUMAChannelNumber;
2918 UCHAR ucDockingPinBit;
2919 UCHAR ucDockingPinPolarity;
3092 …UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal C…
3093 …UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status R…
3100 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3101 UCHAR ucUMAChannelNumber;
3291 UCHAR bfHW_Capable:1;
3292 UCHAR bfHW_EngineID:3;
3293 UCHAR bfI2C_LineMux:4;
3295 UCHAR bfI2C_LineMux:4;
3296 UCHAR bfHW_EngineID:3;
3297 UCHAR bfHW_Capable:1;
3304 UCHAR ucAccess;
3322 UCHAR ucClkMaskShift;
3323 UCHAR ucClkEnShift;
3324 UCHAR ucClkY_Shift;
3325 UCHAR ucClkA_Shift;
3326 UCHAR ucDataMaskShift;
3327 UCHAR ucDataEnShift;
3328 UCHAR ucDataY_Shift;
3329 UCHAR ucDataA_Shift;
3330 UCHAR ucReserved1;
3331 UCHAR ucReserved2;
3440 UCHAR ucH_Border; // From DFP EDID
3441 UCHAR ucV_Border;
3442 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3443 UCHAR ucPadding[3];
3460 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3461 UCHAR ucOverscanRight; // right
3462 UCHAR ucOverscanLeft; // left
3463 UCHAR ucOverscanBottom; // bottom
3464 UCHAR ucOverscanTop; // top
3465 UCHAR ucReserved;
3492 UCHAR ucInternalModeNumber;
3493 UCHAR ucRefreshRate;
3509 UCHAR ucHBorder;
3510 UCHAR ucVBorder;
3512 UCHAR ucInternalModeNumber;
3513 UCHAR ucRefreshRate;
3535 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3536 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3537 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3541 UCHAR ucPanelDefaultRefreshRate;
3542 UCHAR ucPanelIdentification;
3543 UCHAR ucSS_Id;
3555 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3556 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3557 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3561 UCHAR ucPanelDefaultRefreshRate;
3562 UCHAR ucPanelIdentification;
3563 UCHAR ucSS_Id;
3566 UCHAR ucLCDPanel_SpecialHandlingCap;
3567 …UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end …
3568 UCHAR ucReserved[2];
3608 UCHAR ucSupportedRefreshRate;
3609 UCHAR ucMinRefreshRateForDRR;
3629 UCHAR ucLCD_Misc; // Reorganized in V13
3635 UCHAR ucPanelDefaultRefreshRate;
3636 UCHAR ucPanelIdentification;
3637 UCHAR ucSS_Id;
3640 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
3645 …UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel…
3648 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
3649 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
3650 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
3651 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
3653 UCHAR ucOffDelay_in4Ms;
3654 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
3655 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
3656 UCHAR ucReserved1;
3658 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
3659 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
3660 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
3661 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
3664 UCHAR uceDPToLVDSRxId;
3665 UCHAR ucLcdReservd;
3712 UCHAR ucRecordType;
3719 UCHAR ucRecordType;
3720 UCHAR ucRTSValue;
3727 UCHAR ucRecordType;
3738 UCHAR ucRecordType;
3739 …UCHAR ucFakeEDIDLength; // = 128 means EDID lenght is 128 bytes, otherwise the EDID length =…
3740 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements.
3745 UCHAR ucRecordType;
3765 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext.…
3766 UCHAR ucSS_Step;
3767 UCHAR ucSS_Delay;
3768 UCHAR ucSS_Id;
3769 UCHAR ucRecommendedRef_Div;
3770 UCHAR ucSS_Range; //it was reserved for V11
3828 UCHAR ucTV_SuppportedStandard;
3829 UCHAR ucTV_BootUpDefaultStandard;
3830 UCHAR ucExt_TV_ASIC_ID;
3831 UCHAR ucExt_TV_ASIC_SlaveAddr;
3837 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
3838 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
3839 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3840 …UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change acc…
3993 UCHAR ucGpioPinBitShift;
3994 UCHAR ucGPIO_ID;
4035 UCHAR ucSettings;
4036 UCHAR ucReserved;
4078 UCHAR ucBitShift;
4079 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
4081 UCHAR ucMiscInfo;
4082 UCHAR uc480i;
4083 UCHAR uc480p;
4084 UCHAR uc720p;
4085 UCHAR uc1080i;
4086 UCHAR ucLetterBoxMode;
4087 UCHAR ucReserved[3];
4088 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4098 UCHAR ucMiscInfo;
4099 UCHAR uc480i;
4100 UCHAR uc480p;
4101 UCHAR uc720p;
4102 UCHAR uc1080i;
4103 UCHAR ucReserved;
4104 UCHAR ucLetterBoxMode;
4105 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4159 UCHAR ucNumOfDispPath;
4160 UCHAR ucVersion;
4161 UCHAR ucPadding[2];
4175 UCHAR ucNumberOfObjects;
4176 UCHAR ucPadding[3];
4182 UCHAR ucNumberOfSrc;
4184 UCHAR ucNumberOfDst;
4220 UCHAR ucDP_Lane3_Source:2;
4221 UCHAR ucDP_Lane2_Source:2;
4222 UCHAR ucDP_Lane1_Source:2;
4223 UCHAR ucDP_Lane0_Source:2;
4225 UCHAR ucDP_Lane0_Source:2;
4226 UCHAR ucDP_Lane1_Source:2;
4227 UCHAR ucDP_Lane2_Source:2;
4228 UCHAR ucDP_Lane3_Source:2;
4240 UCHAR ucDVI_CLK_Source:2;
4241 UCHAR ucDVI_DATA0_Source:2;
4242 UCHAR ucDVI_DATA1_Source:2;
4243 UCHAR ucDVI_DATA2_Source:2;
4245 UCHAR ucDVI_DATA2_Source:2;
4246 UCHAR ucDVI_DATA1_Source:2;
4247 UCHAR ucDVI_DATA0_Source:2;
4248 UCHAR ucDVI_CLK_Source:2;
4257 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
4258 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
4261 …UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapp…
4265 …UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert…
4282 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
4284 …UCHAR ucChecksum; // a simple Checksum of the sum of…
4285 UCHAR uc3DStereoPinId; // use for eDP panel
4286 UCHAR ucRemoteDisplayConfig;
4287 UCHAR uceDPToLVDSRxId;
4288 …UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_L…
4289 UCHAR Reserved[3]; // for potential expansion
4295 UCHAR ucRecordType; //An emun to indicate the record type
4296 UCHAR ucRecordSize; //The size of the whole record in byte
4330 …UCHAR ucI2CAddr; //The slave address, it's 0 when the record is…
4336 …UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table g…
4337 UCHAR ucPlugged_PinState;
4344 UCHAR ucProtectionFlag;
4345 UCHAR ucReserved;
4358 UCHAR ucNumberOfDevice;
4359 UCHAR ucReserved;
4367 UCHAR ucConfigGPIOID;
4368 …UCHAR ucConfigGPIOState; //Set to 1 when it's active high to en…
4369 UCHAR ucFlowinGPIPID;
4370 UCHAR ucExtInGPIPID;
4376 UCHAR ucCTL1GPIO_ID;
4377 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
4378 UCHAR ucCTL2GPIO_ID;
4379 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
4380 UCHAR ucCTL3GPIO_ID;
4381 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
4382 UCHAR ucCTLFPGA_IN_ID;
4383 UCHAR ucPadding[3];
4389 …UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table g…
4390 …UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is c…
4396 UCHAR ucTMSGPIO_ID;
4397 UCHAR ucTMSGPIOState; //Set to 1 when it's active high
4398 UCHAR ucTCKGPIO_ID;
4399 UCHAR ucTCKGPIOState; //Set to 1 when it's active high
4400 UCHAR ucTDOGPIO_ID;
4401 UCHAR ucTDOGPIOState; //Set to 1 when it's active high
4402 UCHAR ucTDIGPIO_ID;
4403 UCHAR ucTDIGPIOState; //Set to 1 when it's active high
4404 UCHAR ucPadding[2];
4411 …UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_…
4412 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4418 UCHAR ucFlags; // Future expnadibility
4419 …UCHAR ucNumberOfPins; // Number of GPIO pins used to control the obj…
4451 UCHAR ucPadding[2];
4486 UCHAR ucFlowCntlGpioId;
4487 UCHAR ucSwapCntlGpioId;
4488 UCHAR ucConnectedDvoBundle;
4489 UCHAR ucPadding;
4501 …UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_D…
4502 UCHAR ucReserved;
4509 …UCHAR ucMuxType; //decide the number of ucM…
4510 UCHAR ucMuxControlPin;
4511 UCHAR ucMuxState[2]; //for alligment purpose
4517 UCHAR ucMuxType;
4518 UCHAR ucMuxControlPin;
4519 UCHAR ucMuxState[2]; //for alligment purpose
4529 …UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size ar…
4553 UCHAR ucConnectorType;
4554 UCHAR ucPosition;
4568 UCHAR ucLength;
4569 UCHAR ucWidth;
4570 UCHAR ucConnNum;
4571 UCHAR ucReserved;
4583 UCHAR ucNumOfVoltageEntries;
4584 UCHAR ucBytesPerVoltageEntry;
4585 …UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv…
4586 UCHAR ucDefaultVoltageEntry;
4587 UCHAR ucVoltageControlI2cLine;
4588 UCHAR ucVoltageControlAddress;
4589 UCHAR ucVoltageControlOffset;
4596 …UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is pr…
4604 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4605 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
4606 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - Ba…
4607 UCHAR ucReserved;
4608 …UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is pr…
4619 …UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Vol…
4620 UCHAR ucReserved[3];
4626 …UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW …
4627 UCHAR ucVoltageControlI2cLine;
4628 UCHAR ucVoltageControlAddress;
4629 UCHAR ucVoltageControlOffset;
4631 …UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with…
4632 UCHAR ucReserved;
4664 …UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ …
4665 UCHAR ucSize; //Size of Object
4672 … UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4673 UCHAR ucSize; //Size of Object
4692 UCHAR ucLeakageId;
4693 UCHAR ucReserved;
4698 …UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ o…
4699 …UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leaka…
4730 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id
4731 UCHAR ucVoltageControlI2cLine;
4732 UCHAR ucVoltageControlAddress;
4733 UCHAR ucVoltageControlOffset;
4734 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
4735 UCHAR ulReserved[3];
4746 …UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mo…
4747 …UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look …
4748 UCHAR ucPhaseDelay; // phase delay in unit of micro second
4749 UCHAR ucReserved;
4757 UCHAR ucLeakageCntlId; // default is 0
4758 …UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut ta…
4759 UCHAR ucReserved[2];
4775 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31
4776 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31
4796 UCHAR ucProfileId;
4797 UCHAR ucReserved;
4818 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table
4821 UCHAR ucElbVDDC_Num;
4825 UCHAR ucElbVDDCI_Num;
4836 …UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, us…
4837 UCHAR ucEfuseLength; // Efuse bits length,
4846 …UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, us…
4847 UCHAR ucEfuseLength; // Efuse bits length,
4870 UCHAR ucLkgEfuseBitLSB;
4871 UCHAR ucLkgEfuseLength;
4911 UCHAR ucLkgEfuseBitLSB;
4912 UCHAR ucLkgEfuseLength;
4953 UCHAR ucLkgEfuseBitLSB;
4954 UCHAR ucLkgEfuseLength;
4993 UCHAR ucPwrSrcId; // Power source
4994 UCHAR ucPwrSensorType; // GPIO, I2C or none
4995 …UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C det…
4996 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
4997 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
4998 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
4999 UCHAR ucPwrSensActiveState; // high active or low active
5000 UCHAR ucReserve[3]; // reserve
5007 UCHAR asPwrbehave[16];
5060 UCHAR ucHtcTmpLmt;
5061 UCHAR ucHtcHystLmt;
5070 UCHAR ucMemoryType;
5071 UCHAR ucUMAChannelNumber;
5094 UCHAR ulBoostVid_2bit;
5095 UCHAR EnableBoost;
5098 UCHAR ucLvdsMisc;
5099 UCHAR ucLVDSReserved;
5258 UCHAR ucHtcTmpLmt;
5259 UCHAR ucHtcHystLmt;
5268 UCHAR ucMemoryType;
5269 UCHAR ucUMAChannelNumber;
5270 UCHAR strVBIOSMsg[40];
5292 UCHAR ulBoostVid_2bit;
5293 UCHAR EnableBoost;
5296 UCHAR ucLvdsMisc;
5297 UCHAR ucTravisLVDSVolAdjust;
5298 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5299 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5300 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5301 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5302 UCHAR ucLVDSOffToOnDelay_in4Ms;
5303 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5304 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5305 UCHAR ucMinAllowedBL_Level;
5311 UCHAR ucNBDPMEnable;
5312 UCHAR ucReserved[3];
5313 UCHAR ucDPMState0VclkFid;
5314 UCHAR ucDPMState0DclkFid;
5315 UCHAR ucDPMState1VclkFid;
5316 UCHAR ucDPMState1DclkFid;
5317 UCHAR ucDPMState2VclkFid;
5318 UCHAR ucDPMState2DclkFid;
5319 UCHAR ucDPMState3VclkFid;
5320 UCHAR ucDPMState3DclkFid;
5490 UCHAR ucHtcTmpLmt;
5491 UCHAR ucHtcHystLmt;
5499 UCHAR ucMemoryType;
5500 UCHAR ucUMAChannelNumber;
5501 UCHAR strVBIOSMsg[40];
5523 UCHAR ucLvdsMisc;
5524 UCHAR ucTravisLVDSVolAdjust;
5525 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5526 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5527 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5528 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5529 UCHAR ucLVDSOffToOnDelay_in4Ms;
5530 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5531 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5532 UCHAR ucMinAllowedBL_Level;
5699 UCHAR ucI2cRegIndex;
5700 UCHAR ucI2cRegVal;
5716 UCHAR ucHtcTmpLmt;
5717 UCHAR ucHtcHystLmt;
5725 UCHAR ucMemoryType;
5726 UCHAR ucUMAChannelNumber;
5727 UCHAR strVBIOSMsg[40];
5729 UCHAR ucExtHDMIReDrvSlvAddr;
5730 UCHAR ucExtHDMIReDrvRegNum;
5752 UCHAR ucLvdsMisc;
5753 UCHAR ucTravisLVDSVolAdjust;
5754 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5755 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5756 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5757 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5758 UCHAR ucLVDSOffToOnDelay_in4Ms;
5759 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5760 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5761 UCHAR ucMinAllowedBL_Level;
5768 UCHAR ucEDPv1_4VSMode;
5769 UCHAR ucReserved2;
5796 UCHAR ucHtcTmpLmt;
5797 UCHAR ucHtcHystLmt;
5805 UCHAR ucMemoryType;
5806 UCHAR ucUMAChannelNumber;
5807 UCHAR strVBIOSMsg[40];
5829 UCHAR ucLvdsMisc;
5830 UCHAR ucTravisLVDSVolAdjust;
5831 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5832 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5833 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5834 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5835 UCHAR ucLVDSOffToOnDelay_in4Ms;
5836 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5837 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5838 UCHAR ucMinAllowedBL_Level;
5846 UCHAR ucEDPv1_4VSMode;
5847 UCHAR ucReserved2;
5861 …UCHAR ucNunberOfBytes; //Indicates how many b…
5862 …UCHAR ucI2CData[1]; //I2C data in bytes, s…
5870 UCHAR ucSSChipID; //SS chip being used
5871 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
5872 UCHAR ucNumOfI2CDataRecords; //number of data block
5894 UCHAR ucClockIndication; //Indicate which clock source needs SS
5895 …UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Sp…
5896 UCHAR ucReserved[2];
5920 UCHAR ucClockIndication; //Indicate which clock source needs SS
5921 …UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Sp…
5922 UCHAR ucReserved[2];
5951 UCHAR ucClockIndication; //Indicate which clock source needs SS
5952 …UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Sp…
5953 UCHAR ucReserved[2];
6432 UCHAR ucAction; //not define yet
6433 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
6434 UCHAR ucFbDiv; //FB value
6435 UCHAR ucPostDiv; //Post div
6446 UCHAR ucGPIO_ID; //return value, read from GPIO pins
6447 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
6448 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
6449 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
6454 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
6455 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
6456 UCHAR ucTVStandard; //
6457 UCHAR ucPadding[1];
6470 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
6471 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
6472 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
6473 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
6486 UCHAR ucSurface; // Surface 1 or 2
6487 UCHAR ucPadding[3];
6494 UCHAR ucSurface; // Surface 1 or 2
6495 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
6496 UCHAR ucPadding[2];
6503 UCHAR ucSurface; // Surface 1 or 2
6504 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
6513 UCHAR ucColorDepth;
6514 UCHAR ucPixelFormat;
6515 UCHAR ucSurface; // Surface 1 or 2
6516 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
6517 UCHAR ucModeType;
6518 UCHAR ucReserved;
6559 UCHAR ucLutId;
6560 UCHAR ucAction;
6574 UCHAR ucInterruptId;
6575 UCHAR ucServiceId;
6576 UCHAR ucStatus;
6577 UCHAR ucReserved;
6600 UCHAR ucBitShift;
6601 UCHAR ucBitLength;
6614 UCHAR IOAccessSequence[256];
6650 UCHAR ucVMode_Num; //Video mode number
6651 UCHAR ucTV_Mode_Num; //Internal TV mode number
6669 UCHAR ucTV_Mode_Num;
6701 UCHAR ucMemoryType;
6702 UCHAR ucMemoryVendor;
6703 UCHAR ucAdjMCId;
6704 UCHAR ucDynClkId;
6734 …UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saReg…
6841 UCHAR ucRevision;
6842 UCHAR ucChecksum;
6843 UCHAR ucReserved1;
6844 UCHAR ucReserved2;
6862 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or p…
6863 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
6864 …UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory …
6865 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
6866 UCHAR ucRow; // Number of Row,in power of 2;
6867 UCHAR ucColumn; // Number of Column,in power of 2;
6868 UCHAR ucBank; // Nunber of Bank;
6869 UCHAR ucRank; // Number of Rank, in power of 2
6870 UCHAR ucChannelNum; // Number of channel;
6871 …UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7…
6872 …UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID l…
6873 …UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID l…
6874 UCHAR ucReserved[2];
6889 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or p…
6890 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
6891 …UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory …
6892 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
6893 UCHAR ucRow; // Number of Row,in power of 2;
6894 UCHAR ucColumn; // Number of Column,in power of 2;
6895 UCHAR ucBank; // Nunber of Bank;
6896 UCHAR ucRank; // Number of Rank, in power of 2
6897 UCHAR ucChannelNum; // Number of channel;
6898 …UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7…
6899 …UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID l…
6900 …UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID l…
6901 UCHAR ucRefreshRateFactor;
6902 UCHAR ucReserved[3];
6917 UCHAR ucCL; // CAS latency
6918 UCHAR ucWL; // WRITE Latency
6919 UCHAR uctRAS; // tRAS
6920 UCHAR uctRC; // tRC
6921 UCHAR uctRFC; // tRFC
6922 UCHAR uctRCDR; // tRCDR
6923 UCHAR uctRCDW; // tRCDW
6924 UCHAR uctRP; // tRP
6925 UCHAR uctRRD; // tRRD
6926 UCHAR uctWR; // tWR
6927 UCHAR uctWTR; // tWTR
6928 UCHAR uctPDIX; // tPDIX
6929 UCHAR uctFAW; // tFAW
6930 UCHAR uctAOND; // tAOND
6934 …UCHAR ucflag; // flag to control memory timing c…
6935 UCHAR ucReserved;
6947 UCHAR ucCL; // CAS latency
6948 UCHAR ucWL; // WRITE Latency
6949 UCHAR uctRAS; // tRAS
6950 UCHAR uctRC; // tRC
6951 UCHAR uctRFC; // tRFC
6952 UCHAR uctRCDR; // tRCDR
6953 UCHAR uctRCDW; // tRCDW
6954 UCHAR uctRP; // tRP
6955 UCHAR uctRRD; // tRRD
6956 UCHAR uctWR; // tWR
6957 UCHAR uctWTR; // tWTR
6958 UCHAR uctPDIX; // tPDIX
6959 UCHAR uctFAW; // tFAW
6960 UCHAR uctAOND; // tAOND
6961 …UCHAR ucflag; // flag to control memory timing calculation. bi…
6963 UCHAR uctCCDL; //
6964 UCHAR uctCRCRL; //
6965 UCHAR uctCRCWL; //
6966 UCHAR uctCKE; //
6967 UCHAR uctCKRSE; //
6968 UCHAR uctCKRSX; //
6969 UCHAR uctFAW32; //
6970 UCHAR ucMR5lo; //
6971 UCHAR ucMR5hi; //
6972 UCHAR ucTerminator;
6983 UCHAR ucCL; // CAS latency
6984 UCHAR ucWL; // WRITE Latency
6985 UCHAR uctRAS; // tRAS
6986 UCHAR uctRC; // tRC
6987 UCHAR uctRFC; // tRFC
6988 UCHAR uctRCDR; // tRCDR
6989 UCHAR uctRCDW; // tRCDW
6990 UCHAR uctRP; // tRP
6991 UCHAR uctRRD; // tRRD
6992 UCHAR uctWR; // tWR
6993 UCHAR uctWTR; // tWTR
6994 UCHAR uctPDIX; // tPDIX
6995 UCHAR uctFAW; // tFAW
6996 UCHAR uctAOND; // tAOND
6997 …UCHAR ucflag; // flag to control memory timing c…
6999 UCHAR uctCCDL; //
7000 UCHAR uctCRCRL; //
7001 UCHAR uctCRCWL; //
7002 UCHAR uctCKE; //
7003 UCHAR uctCKRSE; //
7004 UCHAR uctCKRSX; //
7005 UCHAR uctFAW32; //
7006 UCHAR ucMR4lo; //
7007 UCHAR ucMR4hi; //
7008 UCHAR ucMR5lo; //
7009 UCHAR ucMR5hi; //
7010 UCHAR ucTerminator;
7011 UCHAR ucReserved;
7026 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3…
7027 …UCHAR ucMemoryVenderID; // Predefined,never change across designs or memor…
7028 UCHAR ucRow; // Number of Row,in power of 2;
7029 UCHAR ucColumn; // Number of Column,in power of 2;
7030 UCHAR ucBank; // Nunber of Bank;
7031 UCHAR ucRank; // Number of Rank, in power of 2
7032 …UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
7033 …UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS …
7034 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
7035 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7036 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7037 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
7048 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or…
7049 UCHAR ucChannelNum; // board dependent parameter:Number of channel;
7050 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
7051 …UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to …
7052 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay,…
7053 …UCHAR ucFlag; // To enable/disable functionalities based on memo…
7071 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin…
7072 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
7073 UCHAR ucChannelNum; // Number of channels present in this module config
7074 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7075 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7076 …UCHAR ucFlag; // To enable/disable functionalities based on m…
7077 …UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2…
7078 UCHAR ucVREFI; // board dependent parameter
7079 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used …
7080 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7081 …UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, u…
7083 UCHAR ucReserved[3];
7094 …UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection ta…
7095 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64…
7096 UCHAR ucReserved2[2];
7113 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin…
7114 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
7115 UCHAR ucChannelNum; // Number of channels present in this module config
7116 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7117 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7118 …UCHAR ucFlag; // To enable/disable functionalities based on m…
7119 …UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2…
7120 UCHAR ucVREFI; // board dependent parameter
7121 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used …
7122 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7123 …UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, u…
7125 UCHAR ucReserved[3];
7130 …UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection ta…
7131 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64…
7132 …UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor…
7133 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7145 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin…
7146 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
7147 UCHAR ucChannelNum; // Number of channels present in this module config
7148 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7149 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7150 …UCHAR ucFlag; // To enable/disable functionalities based on m…
7151 …UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2…
7152 UCHAR ucVREFI; // board dependent parameter
7153 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used …
7154 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7155 …UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, u…
7157 UCHAR ucReserved[3];
7162 …UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection ta…
7163 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64…
7164 …UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor…
7165 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7176 UCHAR ucExtMemoryID; // Current memory module ID
7177 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7178 UCHAR ucChannelNum; // Number of mem. channels supported in this module
7179 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7180 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7181 …UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memo…
7182 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
7183 UCHAR ucVREFI; // Not used.
7184 …UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NP…
7185 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7186 …UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE …
7188 UCHAR ucReserved;
7192 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7193 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7194 …UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, h…
7195 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7207 UCHAR ucExtMemoryID; // Current memory module ID
7208 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7209 UCHAR ucChannelNum; // Number of mem. channels supported in this module
7210 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7211 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7212 …UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[…
7213 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
7214 UCHAR ucVREFI; // Not used.
7217 UCHAR ucMcTunningSetId; // MC phy registers set per.
7218 UCHAR ucRowNum;
7222 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7223 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7224 …UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, h…
7225 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7237 UCHAR ucNumOfVRAMModule;
7247 …UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+…
7248 UCHAR ucNumOfVRAMModule;
7262 …UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, …
7264 UCHAR ucReservde[4];
7265 UCHAR ucNumOfVRAMModule;
7277 …UCHAR ucNumOfVRAMModule; // indicate number of V…
7278 …UCHAR ucMemoryClkPatchTblVer; // version of memory AC…
7279 …UCHAR ucVramModuleVer; // indicate ATOM_VRAM_M…
7280 UCHAR ucReserved;
7293 …UCHAR ucNumOfVRAMModule; // indicate number of V…
7294 …UCHAR ucMemoryClkPatchTblVer; // version of memory AC…
7295 …UCHAR ucVramModuleVer; // indicate ATOM_VRAM_M…
7296 …UCHAR ucMcPhyTileNum; // indicate the MCD til…
7303 UCHAR ucByteRemapCh0;
7304 UCHAR ucByteRemapCh1;
7318 …UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+…
7325 UCHAR ucTrainingLoop;
7326 UCHAR ucReserved[3];
7333 UCHAR ucControl;
7334 UCHAR ucData;
7335 UCHAR ucSatus;
7336 UCHAR ucTemp;
7344 UCHAR ucAct;
7345 UCHAR ucData;
7391 UCHAR VbeSignature[4];
7394 UCHAR Capabilities[4];
7418 UCHAR Reserved[222];
7419 UCHAR OemData[256];
7427 UCHAR RedBPP;
7428 UCHAR GreenBPP;
7429 UCHAR BlueBPP;
7430 UCHAR ReservedBPP;
7433 UCHAR Reserved[14];
7440 UCHAR WinAAttributes; // db ? ; window A attributes
7441 UCHAR WinBAttributes; // db ? ; window B attributes
7452 UCHAR XCharSize; // db ? ; character cell width in pixels
7453 UCHAR YCharSize; // db ? ; character cell height in pixels
7454 UCHAR NumberOfPlanes; // db ? ; number of memory planes
7455 UCHAR BitsPerPixel; // db ? ; bits per pixel
7456 UCHAR NumberOfBanks; // db ? ; number of banks
7457 UCHAR MemoryModel; // db ? ; memory model type
7458 UCHAR BankSize; // db ? ; bank size in KB
7459 UCHAR NumberOfImagePages;// db ? ; number of images
7460 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
7463 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
7464 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
7465 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
7466 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
7467 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
7468 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
7469 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
7470 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
7471 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
7480 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
7481 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
7482 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
7483 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
7484 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
7485 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
7486 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
7487 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
7488 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
7489 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
7491 UCHAR Reserved; // db 190 dup (0)
7547 UCHAR ucTransmitterCmdTblId;
7548 UCHAR ucConfig;
7549 UCHAR ucEncoderID; //available 1st encoder ( default )
7550 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
7551 UCHAR uc2ndEncoderID;
7552 UCHAR ucReserved;
7567 UCHAR ucEncoderID;
7568 UCHAR ucEncoderConfig;
7594 UCHAR ucPpllId;
7595 UCHAR ucPpllAttribute;
7608 UCHAR ucTransmitterCmdTblId;
7609 UCHAR ucConfig;
7610 UCHAR ucEncoderID; // available 1st encoder ( default )
7611 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
7612 UCHAR uc2ndEncoderID;
7613 UCHAR ucReserved;
7623 UCHAR ucDCERevision;
7624 UCHAR ucMaxDispEngineNum;
7625 UCHAR ucMaxActiveDispEngineNum;
7626 UCHAR ucMaxPPLLNum;
7627 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
7628 UCHAR ucDispCaps;
7629 UCHAR ucReserved[2];
7655 UCHAR ucChannelID;
7658 UCHAR ucReplyStatus;
7659 UCHAR ucDelay;
7661 UCHAR ucDataOutLen;
7662 UCHAR ucReserved;
7670 UCHAR ucChannelID;
7673 UCHAR ucReplyStatus;
7674 UCHAR ucDelay;
7676 UCHAR ucDataOutLen;
7677 …UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
7689 UCHAR ucConfig; // for DP training command
7690 UCHAR ucI2cId; // use for GET_SINK_TYPE command
7692 UCHAR ucAction;
7693 UCHAR ucStatus;
7694 UCHAR ucLaneNum;
7695 UCHAR ucReserved[2];
7707 UCHAR ucAuxId;
7708 UCHAR ucAction;
7709 UCHAR ucSinkType; // Iput and Output parameters.
7710 …UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_…
7711 UCHAR ucReserved[2];
7743 UCHAR ucI2CSpeed;
7746 UCHAR ucRegIndex;
7747 UCHAR ucStatus;
7750 UCHAR ucFlag;
7751 UCHAR ucTransBytes;
7752 UCHAR ucSlaveAddr;
7753 UCHAR ucLineNumber;
7768 UCHAR ucCmd; // Input: To tell which action to take
7769 UCHAR ucReserved[3];
7775 UCHAR ucReturnCode; // Output: Return value base on action was taken
7776 UCHAR ucReserved[3];
7798 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
7799 UCHAR ucReserved[3];
7858 UCHAR ucStartBit;
7859 UCHAR ucEndBit;
7864 UCHAR ucEncodeMode;
7865 UCHAR ucPhySel;
7881 UCHAR ucCondition2;
7898 UCHAR ucEncodeMode;
7899 UCHAR ucPhySel;
7905 UCHAR ucEncodeMode;
7906 UCHAR ucPhySel;
7913 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM
7914 UCHAR ucReserved; //reserved
7915 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array
7916 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array
7926 UCHAR PciRomSignature[2];
7927 UCHAR ucPciRomSizeIn512bytes;
7928 UCHAR ucJumpCoreMainInitBIOS;
7930 UCHAR PciReservedSpace[18];
7932 UCHAR Rsvd1d_1a[4];
7934 UCHAR CheckSum[14];
7935 UCHAR ucBiosMsgNumber;
7939 UCHAR ucSpeicalPostImageSizeIn512Bytes;
7940 UCHAR Rsved47_45[3];
7942 UCHAR Rsved4f_4a[6];
7944 UCHAR ucJumpCoreXFuncFarHandler;
7946 UCHAR ucRsved67;
7947 UCHAR ucJumpCoreVFuncFarHandler;
7949 UCHAR Rsved6d_6b[3];
7993 UCHAR ucDAC1_BG_Adjustment;
7994 UCHAR ucDAC1_DAC_Adjustment;
7997 UCHAR ucDAC2_CRT2_BG_Adjustment;
7998 UCHAR ucDAC2_CRT2_DAC_Adjustment;
8001 …UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8002 UCHAR ucDAC2_NTSC_BG_Adjustment;
8003 UCHAR ucDAC2_NTSC_DAC_Adjustment;
8006 …UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8007 UCHAR ucDAC2_CV_BG_Adjustment;
8008 UCHAR ucDAC2_CV_DAC_Adjustment;
8011 …UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
8012 UCHAR ucDAC2_PAL_BG_Adjustment;
8013 UCHAR ucDAC2_PAL_DAC_Adjustment;
8044 UCHAR bfConnectorType:4;
8045 UCHAR bfAssociatedDAC:4;
8047 UCHAR bfAssociatedDAC:4;
8048 UCHAR bfConnectorType:4;
8055 UCHAR ucAccess;
8076 UCHAR ucIntSrcBitmap;
8102 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
8103 UCHAR ucPLL_DutyCycle; // PLL duty cycle control
8104 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
8105 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
8121 UCHAR ucTVStandard; //Same as TV standards defined above,
8122 UCHAR ucPadding[1];
8127 UCHAR ucAttribute; //Same as other digital encoder attributes defined above
8128 UCHAR ucPadding[1];
8142 …UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate d…
8143 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
8167 UCHAR ucXtransimitterID;
8168 …UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,…
8169 …UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's poss…
8171 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
8172 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
8177 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
8178 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
8179 UCHAR ucPadding[2];
8247 UCHAR ucVoltageDropIndex; // index to GPIO table
8248 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
8249 UCHAR ucMinTemperature;
8250 UCHAR ucMaxTemperature;
8251 UCHAR ucNumPciELanes; // number of PCIE lanes
8262 UCHAR ucVoltageDropIndex; // index to GPIO table
8263 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
8264 UCHAR ucMinTemperature;
8265 UCHAR ucMaxTemperature;
8266 UCHAR ucNumPciELanes; // number of PCIE lanes
8277 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
8278 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
8279 UCHAR ucMinTemperature;
8280 UCHAR ucMaxTemperature;
8281 UCHAR ucNumPciELanes; // number of PCIE lanes
8282 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
8303 UCHAR ucOverdriveThermalController;
8304 UCHAR ucOverdriveI2cLine;
8305 UCHAR ucOverdriveIntBitmap;
8306 UCHAR ucOverdriveControllerAddress;
8307 UCHAR ucSizeOfPowerModeEntry;
8308 UCHAR ucNumOfPowerModeEntries;
8315 UCHAR ucOverdriveThermalController;
8316 UCHAR ucOverdriveI2cLine;
8317 UCHAR ucOverdriveIntBitmap;
8318 UCHAR ucOverdriveControllerAddress;
8319 UCHAR ucSizeOfPowerModeEntry;
8320 UCHAR ucNumOfPowerModeEntries;
8327 UCHAR ucOverdriveThermalController;
8328 UCHAR ucOverdriveI2cLine;
8329 UCHAR ucOverdriveIntBitmap;
8330 UCHAR ucOverdriveControllerAddress;
8331 UCHAR ucSizeOfPowerModeEntry;
8332 UCHAR ucNumOfPowerModeEntries;
8467 UCHAR ucRevision; // Holes set revision
8468 UCHAR ucAlgorithm; // Hash algorithm
8469 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )
8470 UCHAR ucReserved;
8480 UCHAR ucholesNo; // number of holes that follow
8496 UCHAR Revision;
8497 UCHAR Checksum;
8498 UCHAR OemId[6];
8499 UCHAR OemTableId[8]; //UINT64 OemTableId;
8520 UCHAR TableUUID[16]; //0x24
8541 UCHAR VbiosContent[1];
8546 UCHAR Lib1Content[1];