353 	struct pm4__set_config_reg *packets_vec;  in dbgdev_address_watch_diq()  local
395 	packets_vec = (struct pm4__set_config_reg *) (packet_buff_uint);  in dbgdev_address_watch_diq()
397 	packets_vec[0].header.count = 1;  in dbgdev_address_watch_diq()
398 	packets_vec[0].header.opcode = IT_SET_CONFIG_REG;  in dbgdev_address_watch_diq()
399 	packets_vec[0].header.type = PM4_TYPE_3;  in dbgdev_address_watch_diq()
400 	packets_vec[0].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;  in dbgdev_address_watch_diq()
401 	packets_vec[0].bitfields2.insert_vmid = 1;  in dbgdev_address_watch_diq()
402 	packets_vec[1].ordinal1 = packets_vec[0].ordinal1;  in dbgdev_address_watch_diq()
403 	packets_vec[1].bitfields2.insert_vmid = 0;  in dbgdev_address_watch_diq()
404 	packets_vec[2].ordinal1 = packets_vec[0].ordinal1;  in dbgdev_address_watch_diq()
405 	packets_vec[2].bitfields2.insert_vmid = 0;  in dbgdev_address_watch_diq()
406 	packets_vec[3].ordinal1 = packets_vec[0].ordinal1;  in dbgdev_address_watch_diq()
407 	packets_vec[3].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;  in dbgdev_address_watch_diq()
408 	packets_vec[3].bitfields2.insert_vmid = 1;  in dbgdev_address_watch_diq()
447 		packets_vec[0].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
450 		packets_vec[0].reg_data[0] = cntl.u32All;  in dbgdev_address_watch_diq()
460 		packets_vec[1].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
462 		packets_vec[1].reg_data[0] = addrHi.u32All;  in dbgdev_address_watch_diq()
472 		packets_vec[2].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
474 		packets_vec[2].reg_data[0] = addrLo.u32All;  in dbgdev_address_watch_diq()
490 		packets_vec[3].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
492 		packets_vec[3].reg_data[0] = cntl.u32All;  in dbgdev_address_watch_diq()
620 	struct pm4__set_config_reg *packets_vec;  in dbgdev_wave_control_diq()  local
678 	packets_vec =  (struct pm4__set_config_reg *) packet_buff_uint;  in dbgdev_wave_control_diq()
679 	packets_vec[0].header.count = 1;  in dbgdev_wave_control_diq()
680 	packets_vec[0].header.opcode = IT_SET_UCONFIG_REG;  in dbgdev_wave_control_diq()
681 	packets_vec[0].header.type = PM4_TYPE_3;  in dbgdev_wave_control_diq()
682 	packets_vec[0].bitfields2.reg_offset =  in dbgdev_wave_control_diq()
686 	packets_vec[0].bitfields2.insert_vmid = 0;  in dbgdev_wave_control_diq()
687 	packets_vec[0].reg_data[0] = reg_gfx_index.u32All;  in dbgdev_wave_control_diq()
689 	packets_vec[1].header.count = 1;  in dbgdev_wave_control_diq()
690 	packets_vec[1].header.opcode = IT_SET_CONFIG_REG;  in dbgdev_wave_control_diq()
691 	packets_vec[1].header.type = PM4_TYPE_3;  in dbgdev_wave_control_diq()
692 	packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) -  in dbgdev_wave_control_diq()
695 	packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET;  in dbgdev_wave_control_diq()
696 	packets_vec[1].bitfields2.insert_vmid = 1;  in dbgdev_wave_control_diq()
697 	packets_vec[1].reg_data[0] = reg_sq_cmd.u32All;  in dbgdev_wave_control_diq()
707 	packets_vec[2].ordinal1 = packets_vec[0].ordinal1;  in dbgdev_wave_control_diq()
708 	packets_vec[2].bitfields2.reg_offset =  in dbgdev_wave_control_diq()
712 	packets_vec[2].bitfields2.insert_vmid = 0;  in dbgdev_wave_control_diq()
713 	packets_vec[2].reg_data[0] = reg_gfx_index.u32All;  in dbgdev_wave_control_diq()