534 		reg_sq_cmd.bits.check_vmid = 1;  in dbgdev_wave_control_set_registers()
535 		reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD;  in dbgdev_wave_control_set_registers()
536 		reg_sq_cmd.bits.wave_id = pMsg->ui32.WaveId;  in dbgdev_wave_control_set_registers()
537 		reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_SINGLE;  in dbgdev_wave_control_set_registers()
539 		reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray;  in dbgdev_wave_control_set_registers()
540 		reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine;  in dbgdev_wave_control_set_registers()
541 		reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU;  in dbgdev_wave_control_set_registers()
548 		reg_gfx_index.bits.sh_broadcast_writes = 1;  in dbgdev_wave_control_set_registers()
549 		reg_gfx_index.bits.se_broadcast_writes = 1;  in dbgdev_wave_control_set_registers()
550 		reg_gfx_index.bits.instance_broadcast_writes = 1;  in dbgdev_wave_control_set_registers()
552 		reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;  in dbgdev_wave_control_set_registers()
559 		reg_sq_cmd.bits.check_vmid = 1;  in dbgdev_wave_control_set_registers()
560 		reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;  in dbgdev_wave_control_set_registers()
562 		reg_gfx_index.bits.sh_index = pMsg->ui32.ShaderArray;  in dbgdev_wave_control_set_registers()
563 		reg_gfx_index.bits.se_index = pMsg->ui32.ShaderEngine;  in dbgdev_wave_control_set_registers()
564 		reg_gfx_index.bits.instance_index = pMsg->ui32.HSACU;  in dbgdev_wave_control_set_registers()
574 		reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_HALT;  in dbgdev_wave_control_set_registers()
578 		reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_RESUME;  in dbgdev_wave_control_set_registers()
582 		reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL;  in dbgdev_wave_control_set_registers()
586 		reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_DEBUG;  in dbgdev_wave_control_set_registers()
591 			reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_TRAP;  in dbgdev_wave_control_set_registers()
592 			reg_sq_cmd.bits.trap_id = wac_info->trapId;  in dbgdev_wave_control_set_registers()
635 	reg_sq_cmd.bits.vm_id = 0;  in dbgdev_wave_control_diq()
702 	reg_gfx_index.bits.sh_broadcast_writes = 1;  in dbgdev_wave_control_diq()
703 	reg_gfx_index.bits.instance_broadcast_writes = 1;  in dbgdev_wave_control_diq()
704 	reg_gfx_index.bits.se_broadcast_writes = 1;  in dbgdev_wave_control_diq()
758 	reg_sq_cmd.bits.vm_id = pdd->qpd.vmid;  in dbgdev_wave_control_nodiq()
851 	reg_sq_cmd.bits.vm_id = vmid;  in dbgdev_wave_reset_wavefronts()