95 	ib_packet->bitfields2.ib_base_lo = largep->u.low_part >> 2;  in dbgdev_diq_submit_ib()
133 	rm_packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;  in dbgdev_diq_submit_ib()
134 	rm_packet->bitfields2.event_index =  in dbgdev_diq_submit_ib()
137 	rm_packet->bitfields2.cache_policy = cache_policy___release_mem__lru;  in dbgdev_diq_submit_ib()
138 	rm_packet->bitfields2.atc = 0;  in dbgdev_diq_submit_ib()
139 	rm_packet->bitfields2.tc_wb_action_ena = 1;  in dbgdev_diq_submit_ib()
400 	packets_vec[0].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;  in dbgdev_address_watch_diq()
401 	packets_vec[0].bitfields2.insert_vmid = 1;  in dbgdev_address_watch_diq()
403 	packets_vec[1].bitfields2.insert_vmid = 0;  in dbgdev_address_watch_diq()
405 	packets_vec[2].bitfields2.insert_vmid = 0;  in dbgdev_address_watch_diq()
407 	packets_vec[3].bitfields2.vmid_shift = ADDRESS_WATCH_CNTL_OFFSET;  in dbgdev_address_watch_diq()
408 	packets_vec[3].bitfields2.insert_vmid = 1;  in dbgdev_address_watch_diq()
447 		packets_vec[0].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
460 		packets_vec[1].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
472 		packets_vec[2].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
490 		packets_vec[3].bitfields2.reg_offset =  in dbgdev_address_watch_diq()
682 	packets_vec[0].bitfields2.reg_offset =  in dbgdev_wave_control_diq()
686 	packets_vec[0].bitfields2.insert_vmid = 0;  in dbgdev_wave_control_diq()
692 	packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) -  in dbgdev_wave_control_diq()
695 	packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET;  in dbgdev_wave_control_diq()
696 	packets_vec[1].bitfields2.insert_vmid = 1;  in dbgdev_wave_control_diq()
708 	packets_vec[2].bitfields2.reg_offset =  in dbgdev_wave_control_diq()
712 	packets_vec[2].bitfields2.insert_vmid = 0;  in dbgdev_wave_control_diq()