256 		cntl->bitfields.mask =  in dbgdev_address_watch_set_registers()
260 		cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK;  in dbgdev_address_watch_set_registers()
264 	addrHi->bitfields.addr = addr.u.high_part &  in dbgdev_address_watch_set_registers()
266 	addrLo->bitfields.addr =  in dbgdev_address_watch_set_registers()
269 	cntl->bitfields.mode = adw_info->watch_mode[index];  in dbgdev_address_watch_set_registers()
270 	cntl->bitfields.vmid = (uint32_t) vmid;  in dbgdev_address_watch_set_registers()
274 	pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask);  in dbgdev_address_watch_set_registers()
276 			addrHi->bitfields.addr);  in dbgdev_address_watch_set_registers()
278 			addrLo->bitfields.addr);  in dbgdev_address_watch_set_registers()
324 				addrLo.bitfields.addr);  in dbgdev_address_watch_nodiq()
326 				addrHi.bitfields.addr);  in dbgdev_address_watch_nodiq()
328 				addrHi.bitfields.addr);  in dbgdev_address_watch_nodiq()
330 				cntl.bitfields.mask);  in dbgdev_address_watch_nodiq()
332 				cntl.bitfields.mode);  in dbgdev_address_watch_nodiq()
334 				cntl.bitfields.vmid);  in dbgdev_address_watch_nodiq()
336 				cntl.bitfields.atc);  in dbgdev_address_watch_nodiq()
426 				addrLo.bitfields.addr);  in dbgdev_address_watch_diq()
428 				addrHi.bitfields.addr);  in dbgdev_address_watch_diq()
430 				cntl.bitfields.mask);  in dbgdev_address_watch_diq()
432 				cntl.bitfields.mode);  in dbgdev_address_watch_diq()
434 				cntl.bitfields.vmid);  in dbgdev_address_watch_diq()
436 				cntl.bitfields.atc);  in dbgdev_address_watch_diq()
478 			cntl.bitfields.valid = 1;  in dbgdev_address_watch_diq()
480 			cntl.bitfields.valid = 0;  in dbgdev_address_watch_diq()
646 	pr_debug("\t\t chk_vmid  is : %u\n", reg_sq_cmd.bitfields.check_vmid);  in dbgdev_wave_control_diq()
647 	pr_debug("\t\t command   is : %u\n", reg_sq_cmd.bitfields.cmd);  in dbgdev_wave_control_diq()
648 	pr_debug("\t\t queue id  is : %u\n", reg_sq_cmd.bitfields.queue_id);  in dbgdev_wave_control_diq()
649 	pr_debug("\t\t simd id   is : %u\n", reg_sq_cmd.bitfields.simd_id);  in dbgdev_wave_control_diq()
650 	pr_debug("\t\t mode      is : %u\n", reg_sq_cmd.bitfields.mode);  in dbgdev_wave_control_diq()
651 	pr_debug("\t\t vm_id     is : %u\n", reg_sq_cmd.bitfields.vm_id);  in dbgdev_wave_control_diq()
652 	pr_debug("\t\t wave_id   is : %u\n", reg_sq_cmd.bitfields.wave_id);  in dbgdev_wave_control_diq()
655 			reg_gfx_index.bitfields.instance_broadcast_writes);  in dbgdev_wave_control_diq()
657 			reg_gfx_index.bitfields.instance_index);  in dbgdev_wave_control_diq()
659 			reg_gfx_index.bitfields.se_broadcast_writes);  in dbgdev_wave_control_diq()
660 	pr_debug("\t\t se_ind    is : %u\n", reg_gfx_index.bitfields.se_index);  in dbgdev_wave_control_diq()
661 	pr_debug("\t\t sh_ind    is : %u\n", reg_gfx_index.bitfields.sh_index);  in dbgdev_wave_control_diq()
663 			reg_gfx_index.bitfields.sh_broadcast_writes);  in dbgdev_wave_control_diq()
769 	pr_debug("\t\t chk_vmid  is : %u\n", reg_sq_cmd.bitfields.check_vmid);  in dbgdev_wave_control_nodiq()
770 	pr_debug("\t\t command   is : %u\n", reg_sq_cmd.bitfields.cmd);  in dbgdev_wave_control_nodiq()
771 	pr_debug("\t\t queue id  is : %u\n", reg_sq_cmd.bitfields.queue_id);  in dbgdev_wave_control_nodiq()
772 	pr_debug("\t\t simd id   is : %u\n", reg_sq_cmd.bitfields.simd_id);  in dbgdev_wave_control_nodiq()
773 	pr_debug("\t\t mode      is : %u\n", reg_sq_cmd.bitfields.mode);  in dbgdev_wave_control_nodiq()
774 	pr_debug("\t\t vm_id     is : %u\n", reg_sq_cmd.bitfields.vm_id);  in dbgdev_wave_control_nodiq()
775 	pr_debug("\t\t wave_id   is : %u\n", reg_sq_cmd.bitfields.wave_id);  in dbgdev_wave_control_nodiq()
778 			reg_gfx_index.bitfields.instance_broadcast_writes);  in dbgdev_wave_control_nodiq()
780 			reg_gfx_index.bitfields.instance_index);  in dbgdev_wave_control_nodiq()
782 			reg_gfx_index.bitfields.se_broadcast_writes);  in dbgdev_wave_control_nodiq()
783 	pr_debug("\t\t se_ind    is : %u\n", reg_gfx_index.bitfields.se_index);  in dbgdev_wave_control_nodiq()
784 	pr_debug("\t\t sh_ind    is : %u\n", reg_gfx_index.bitfields.sh_index);  in dbgdev_wave_control_nodiq()
786 			reg_gfx_index.bitfields.sh_broadcast_writes);  in dbgdev_wave_control_nodiq()