Lines Matching refs:uint8_t

50 	uint8_t		revision;
51 	uint8_t		checksum;
52 	uint8_t		oem_id[CRAT_OEMID_LENGTH];
53 	uint8_t		oem_table_id[CRAT_OEMTABLEID_LENGTH];
59 	uint8_t		reserved[CRAT_RESERVED_LENGTH];
93 	uint8_t		type;
94 	uint8_t		length;
105 	uint8_t		wave_front_size;
106 	uint8_t		num_banks;
108 	uint8_t		num_arrays;
109 	uint8_t		num_cu_per_array;
110 	uint8_t		num_simd_per_cu;
111 	uint8_t		max_slots_scatch_cu;
112 	uint8_t		reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];
126 	uint8_t		type;
127 	uint8_t		length;
136 	uint8_t		reserved2[CRAT_MEMORY_RESERVED_LENGTH];
152 	uint8_t		type;
153 	uint8_t		length;
157 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
159 	uint8_t		cache_level;
160 	uint8_t		lines_per_tag;
162 	uint8_t		associativity;
163 	uint8_t		cache_properties;
165 	uint8_t		reserved2[CRAT_CACHE_RESERVED_LENGTH];
181 	uint8_t		type;
182 	uint8_t		length;
186 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
188 	uint8_t		data_tlb_associativity_2mb;
189 	uint8_t		data_tlb_size_2mb;
190 	uint8_t		instruction_tlb_associativity_2mb;
191 	uint8_t		instruction_tlb_size_2mb;
192 	uint8_t		data_tlb_associativity_4k;
193 	uint8_t		data_tlb_size_4k;
194 	uint8_t		instruction_tlb_associativity_4k;
195 	uint8_t		instruction_tlb_size_4k;
196 	uint8_t		data_tlb_associativity_1gb;
197 	uint8_t		data_tlb_size_1gb;
198 	uint8_t		instruction_tlb_associativity_1gb;
199 	uint8_t		instruction_tlb_size_1gb;
200 	uint8_t		reserved2[CRAT_TLB_RESERVED_LENGTH];
212 	uint8_t		type;
213 	uint8_t		length;
217 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
219 	uint8_t		reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];
241 	uint8_t		type;
242 	uint8_t		length;
247 	uint8_t		io_interface_type;
248 	uint8_t		version_major;
255 	uint8_t		reserved2[CRAT_IOLINK_RESERVED_LENGTH];
265 	uint8_t		type;
266 	uint8_t		length;
280 	uint8_t		revision;
281 	uint8_t		checksum;
282 	uint8_t		oem_id[CDIT_OEMID_LENGTH];
283 	uint8_t		oem_table_id[CDIT_OEMTABLEID_LENGTH];
289 	uint8_t		entry[1];