291 	u32 tmp;  in vi_get_xclk()  local
296 	tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);  in vi_get_xclk()
297 	if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))  in vi_get_xclk()
300 	tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);  in vi_get_xclk()
301 	if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))  in vi_get_xclk()
594 	u32 tmp;  in vi_gpu_check_soft_reset()  local
597 	tmp = RREG32(mmGRBM_STATUS);  in vi_gpu_check_soft_reset()
598 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |  in vi_gpu_check_soft_reset()
606 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))  in vi_gpu_check_soft_reset()
610 	tmp = RREG32(mmGRBM_STATUS2);  in vi_gpu_check_soft_reset()
611 	if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)  in vi_gpu_check_soft_reset()
614 	if (tmp & (GRBM_STATUS2__CPF_BUSY_MASK |  in vi_gpu_check_soft_reset()
620 	tmp = RREG32(mmSRBM_STATUS2);  in vi_gpu_check_soft_reset()
621 	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)  in vi_gpu_check_soft_reset()
624 	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)  in vi_gpu_check_soft_reset()
628 	tmp = RREG32(mmSRBM_STATUS);  in vi_gpu_check_soft_reset()
630 	if (tmp & SRBM_STATUS__IH_BUSY_MASK)  in vi_gpu_check_soft_reset()
633 	if (tmp & SRBM_STATUS__SEM_BUSY_MASK)  in vi_gpu_check_soft_reset()
636 	if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)  in vi_gpu_check_soft_reset()
640 		if (tmp & (SRBM_STATUS__UVD_RQ_PENDING_MASK |  in vi_gpu_check_soft_reset()
645 	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)  in vi_gpu_check_soft_reset()
648 	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |  in vi_gpu_check_soft_reset()
653 	tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);  in vi_gpu_check_soft_reset()
654 	if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))  in vi_gpu_check_soft_reset()
659 		tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);  in vi_gpu_check_soft_reset()
660 		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))  in vi_gpu_check_soft_reset()
666 		tmp = RREG32(mmVCE_STATUS);  in vi_gpu_check_soft_reset()
667 		if (tmp & VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK)  in vi_gpu_check_soft_reset()
669 		if (tmp & VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK)  in vi_gpu_check_soft_reset()
701 	u32 tmp;  in vi_gpu_soft_reset()  local
721 	tmp = RREG32(mmCP_ME_CNTL);  in vi_gpu_soft_reset()
722 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);  in vi_gpu_soft_reset()
723 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);  in vi_gpu_soft_reset()
724 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);  in vi_gpu_soft_reset()
725 	WREG32(mmCP_ME_CNTL, tmp);  in vi_gpu_soft_reset()
728 	tmp = RREG32(mmCP_MEC_CNTL);  in vi_gpu_soft_reset()
729 	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);  in vi_gpu_soft_reset()
730 	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);  in vi_gpu_soft_reset()
731 	WREG32(mmCP_MEC_CNTL, tmp);  in vi_gpu_soft_reset()
735 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);  in vi_gpu_soft_reset()
736 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);  in vi_gpu_soft_reset()
737 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in vi_gpu_soft_reset()
741 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);  in vi_gpu_soft_reset()
742 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);  in vi_gpu_soft_reset()
743 		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in vi_gpu_soft_reset()
816 		tmp = RREG32(mmGRBM_SOFT_RESET);  in vi_gpu_soft_reset()
817 		tmp |= grbm_soft_reset;  in vi_gpu_soft_reset()
818 		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);  in vi_gpu_soft_reset()
819 		WREG32(mmGRBM_SOFT_RESET, tmp);  in vi_gpu_soft_reset()
820 		tmp = RREG32(mmGRBM_SOFT_RESET);  in vi_gpu_soft_reset()
824 		tmp &= ~grbm_soft_reset;  in vi_gpu_soft_reset()
825 		WREG32(mmGRBM_SOFT_RESET, tmp);  in vi_gpu_soft_reset()
826 		tmp = RREG32(mmGRBM_SOFT_RESET);  in vi_gpu_soft_reset()
830 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vi_gpu_soft_reset()
831 		tmp |= srbm_soft_reset;  in vi_gpu_soft_reset()
832 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in vi_gpu_soft_reset()
833 		WREG32(mmSRBM_SOFT_RESET, tmp);  in vi_gpu_soft_reset()
834 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vi_gpu_soft_reset()
838 		tmp &= ~srbm_soft_reset;  in vi_gpu_soft_reset()
839 		WREG32(mmSRBM_SOFT_RESET, tmp);  in vi_gpu_soft_reset()
840 		tmp = RREG32(mmSRBM_SOFT_RESET);  in vi_gpu_soft_reset()
855 	u32 tmp, i;  in vi_gpu_pci_config_reset()  local
864 	tmp = RREG32(mmCP_ME_CNTL);  in vi_gpu_pci_config_reset()
865 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);  in vi_gpu_pci_config_reset()
866 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);  in vi_gpu_pci_config_reset()
867 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);  in vi_gpu_pci_config_reset()
868 	WREG32(mmCP_ME_CNTL, tmp);  in vi_gpu_pci_config_reset()
871 	tmp = RREG32(mmCP_MEC_CNTL);  in vi_gpu_pci_config_reset()
872 	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);  in vi_gpu_pci_config_reset()
873 	tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);  in vi_gpu_pci_config_reset()
874 	WREG32(mmCP_MEC_CNTL, tmp);  in vi_gpu_pci_config_reset()
885 	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);  in vi_gpu_pci_config_reset()
886 	tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);  in vi_gpu_pci_config_reset()
887 	WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in vi_gpu_pci_config_reset()
890 	tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);  in vi_gpu_pci_config_reset()
891 	tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);  in vi_gpu_pci_config_reset()
892 	WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in vi_gpu_pci_config_reset()
926 	u32 tmp = RREG32(mmBIOS_SCRATCH_3);  in vi_set_bios_scratch_engine_hung()  local
929 		tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;  in vi_set_bios_scratch_engine_hung()
931 		tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;  in vi_set_bios_scratch_engine_hung()
933 	WREG32(mmBIOS_SCRATCH_3, tmp);  in vi_set_bios_scratch_engine_hung()
976 	uint32_t tmp;  in vi_set_uvd_clock()  local
984 	tmp = RREG32_SMC(cntl_reg);  in vi_set_uvd_clock()
985 	tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |  in vi_set_uvd_clock()
987 	tmp |= dividers.post_divider;  in vi_set_uvd_clock()
988 	WREG32_SMC(cntl_reg, tmp);  in vi_set_uvd_clock()
1057 	u32 tmp;  in vi_enable_doorbell_aperture()  local
1063 	tmp = RREG32(mmBIF_DOORBELL_APER_EN);  in vi_enable_doorbell_aperture()
1065 		tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);  in vi_enable_doorbell_aperture()
1067 		tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);  in vi_enable_doorbell_aperture()
1069 	WREG32(mmBIF_DOORBELL_APER_EN, tmp);  in vi_enable_doorbell_aperture()