79 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)  in vi_pcie_rreg()  argument
84 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in vi_pcie_rreg()
88 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in vi_pcie_rreg()
92 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in vi_pcie_wreg()  argument
96 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);  in vi_pcie_wreg()
101 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);  in vi_pcie_wreg()
104 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)  in vi_smc_rreg()  argument
109 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in vi_smc_rreg()
112 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in vi_smc_rreg()
116 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in vi_smc_wreg()  argument
120 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in vi_smc_wreg()
123 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in vi_smc_wreg()
130 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)  in cz_smc_rreg()  argument
135 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in cz_smc_rreg()
138 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in cz_smc_rreg()
142 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in cz_smc_wreg()  argument
146 	spin_lock_irqsave(&adev->smc_idx_lock, flags);  in cz_smc_wreg()
149 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);  in cz_smc_wreg()
152 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)  in vi_uvd_ctx_rreg()  argument
157 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in vi_uvd_ctx_rreg()
160 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in vi_uvd_ctx_rreg()
164 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in vi_uvd_ctx_wreg()  argument
168 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);  in vi_uvd_ctx_wreg()
171 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);  in vi_uvd_ctx_wreg()
174 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)  in vi_didt_rreg()  argument
179 	spin_lock_irqsave(&adev->didt_idx_lock, flags);  in vi_didt_rreg()
182 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);  in vi_didt_rreg()
186 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)  in vi_didt_wreg()  argument
190 	spin_lock_irqsave(&adev->didt_idx_lock, flags);  in vi_didt_wreg()
193 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);  in vi_didt_wreg()
243 static void vi_init_golden_registers(struct amdgpu_device *adev)  in vi_init_golden_registers()  argument
246 	mutex_lock(&adev->grbm_idx_mutex);  in vi_init_golden_registers()
248 	switch (adev->asic_type) {  in vi_init_golden_registers()
250 		amdgpu_program_register_sequence(adev,  in vi_init_golden_registers()
255 		amdgpu_program_register_sequence(adev,  in vi_init_golden_registers()
260 		amdgpu_program_register_sequence(adev,  in vi_init_golden_registers()
265 		amdgpu_program_register_sequence(adev,  in vi_init_golden_registers()
270 		amdgpu_program_register_sequence(adev,  in vi_init_golden_registers()
277 	mutex_unlock(&adev->grbm_idx_mutex);  in vi_init_golden_registers()
288 static u32 vi_get_xclk(struct amdgpu_device *adev)  in vi_get_xclk()  argument
290 	u32 reference_clock = adev->clock.spll.reference_freq;  in vi_get_xclk()
293 	if (adev->flags & AMD_IS_APU)  in vi_get_xclk()
320 void vi_srbm_select(struct amdgpu_device *adev,  in vi_srbm_select()  argument
331 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)  in vi_vga_set_state()  argument
336 static bool vi_read_disabled_bios(struct amdgpu_device *adev)  in vi_read_disabled_bios()  argument
346 	if (adev->mode_info.num_crtc) {  in vi_read_disabled_bios()
355 	if (adev->mode_info.num_crtc) {  in vi_read_disabled_bios()
368 	r = amdgpu_read_bios(adev);  in vi_read_disabled_bios()
372 	if (adev->mode_info.num_crtc) {  in vi_read_disabled_bios()
471 static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,  in vi_read_indexed_register()  argument
476 	mutex_lock(&adev->grbm_idx_mutex);  in vi_read_indexed_register()
478 		gfx_v8_0_select_se_sh(adev, se_num, sh_num);  in vi_read_indexed_register()
483 		gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);  in vi_read_indexed_register()
484 	mutex_unlock(&adev->grbm_idx_mutex);  in vi_read_indexed_register()
488 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,  in vi_read_register()  argument
496 	switch (adev->asic_type) {  in vi_read_register()
519 					vi_read_indexed_register(adev, se_num,  in vi_read_register()
532 				vi_read_indexed_register(adev, se_num,  in vi_read_register()
540 static void vi_print_gpu_status_regs(struct amdgpu_device *adev)  in vi_print_gpu_status_regs()  argument
542 	dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",  in vi_print_gpu_status_regs()
544 	dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",  in vi_print_gpu_status_regs()
546 	dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",  in vi_print_gpu_status_regs()
548 	dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",  in vi_print_gpu_status_regs()
550 	dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",  in vi_print_gpu_status_regs()
552 	dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",  in vi_print_gpu_status_regs()
554 	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",  in vi_print_gpu_status_regs()
556 	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",  in vi_print_gpu_status_regs()
558 	dev_info(adev->dev, "  SDMA0_STATUS_REG   = 0x%08X\n",  in vi_print_gpu_status_regs()
560 	if (adev->sdma.num_instances > 1) {  in vi_print_gpu_status_regs()
561 		dev_info(adev->dev, "  SDMA1_STATUS_REG   = 0x%08X\n",  in vi_print_gpu_status_regs()
564 	dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));  in vi_print_gpu_status_regs()
565 	dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",  in vi_print_gpu_status_regs()
567 	dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",  in vi_print_gpu_status_regs()
569 	dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",  in vi_print_gpu_status_regs()
571 	dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",  in vi_print_gpu_status_regs()
573 	dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",  in vi_print_gpu_status_regs()
575 	dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));  in vi_print_gpu_status_regs()
576 	dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));  in vi_print_gpu_status_regs()
577 	dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",  in vi_print_gpu_status_regs()
579 	dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));  in vi_print_gpu_status_regs()
591 u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev)  in vi_gpu_check_soft_reset()  argument
639 	if (adev->asic_type != CHIP_TOPAZ) {  in vi_gpu_check_soft_reset()
658 	if (adev->sdma.num_instances > 1) {  in vi_gpu_check_soft_reset()
665 	if (adev->asic_type != CHIP_TOPAZ) {  in vi_gpu_check_soft_reset()
674 	if (adev->asic_type != CHIP_TOPAZ) {  in vi_gpu_check_soft_reset()
675 		if (amdgpu_display_is_display_hung(adev))  in vi_gpu_check_soft_reset()
697 static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)  in vi_gpu_soft_reset()  argument
706 	dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in vi_gpu_soft_reset()
708 	vi_print_gpu_status_regs(adev);  in vi_gpu_soft_reset()
709 	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",  in vi_gpu_soft_reset()
711 	dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",  in vi_gpu_soft_reset()
746 	gmc_v8_0_mc_stop(adev, &save);  in vi_gpu_soft_reset()
747 	if (amdgpu_asic_wait_for_mc_idle(adev)) {  in vi_gpu_soft_reset()
748 		dev_warn(adev->dev, "Wait for MC idle timedout !\n");  in vi_gpu_soft_reset()
809 	if (!(adev->flags & AMD_IS_APU)) {  in vi_gpu_soft_reset()
818 		dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);  in vi_gpu_soft_reset()
832 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in vi_gpu_soft_reset()
846 	gmc_v8_0_mc_resume(adev, &save);  in vi_gpu_soft_reset()
849 	vi_print_gpu_status_regs(adev);  in vi_gpu_soft_reset()
852 static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)  in vi_gpu_pci_config_reset()  argument
857 	dev_info(adev->dev, "GPU pci config reset\n");  in vi_gpu_pci_config_reset()
903 	gmc_v8_0_mc_stop(adev, &save);  in vi_gpu_pci_config_reset()
904 	if (amdgpu_asic_wait_for_mc_idle(adev)) {  in vi_gpu_pci_config_reset()
905 		dev_warn(adev->dev, "Wait for MC idle timed out !\n");  in vi_gpu_pci_config_reset()
909 	pci_clear_master(adev->pdev);  in vi_gpu_pci_config_reset()
911 	amdgpu_pci_config_reset(adev);  in vi_gpu_pci_config_reset()
916 	for (i = 0; i < adev->usec_timeout; i++) {  in vi_gpu_pci_config_reset()
924 static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)  in vi_set_bios_scratch_engine_hung()  argument
945 static int vi_asic_reset(struct amdgpu_device *adev)  in vi_asic_reset()  argument
949 	reset_mask = vi_gpu_check_soft_reset(adev);  in vi_asic_reset()
952 		vi_set_bios_scratch_engine_hung(adev, true);  in vi_asic_reset()
955 	vi_gpu_soft_reset(adev, reset_mask);  in vi_asic_reset()
957 	reset_mask = vi_gpu_check_soft_reset(adev);  in vi_asic_reset()
961 		vi_gpu_pci_config_reset(adev);  in vi_asic_reset()
963 	reset_mask = vi_gpu_check_soft_reset(adev);  in vi_asic_reset()
966 		vi_set_bios_scratch_engine_hung(adev, false);  in vi_asic_reset()
971 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,  in vi_set_uvd_clock()  argument
978 	r = amdgpu_atombios_get_clock_dividers(adev,  in vi_set_uvd_clock()
1001 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)  in vi_set_uvd_clocks()  argument
1005 	r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);  in vi_set_uvd_clocks()
1009 	r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);  in vi_set_uvd_clocks()
1014 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)  in vi_set_vce_clocks()  argument
1021 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)  in vi_pcie_gen3_enable()  argument
1026 	if (pci_is_root_bus(adev->pdev->bus))  in vi_pcie_gen3_enable()
1032 	if (adev->flags & AMD_IS_APU)  in vi_pcie_gen3_enable()
1035 	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);  in vi_pcie_gen3_enable()
1045 static void vi_program_aspm(struct amdgpu_device *adev)  in vi_program_aspm()  argument
1054 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,  in vi_enable_doorbell_aperture()  argument
1060 	if (adev->flags & AMD_IS_APU)  in vi_enable_doorbell_aperture()
1324 int vi_set_ip_blocks(struct amdgpu_device *adev)  in vi_set_ip_blocks()  argument
1326 	switch (adev->asic_type) {  in vi_set_ip_blocks()
1328 		adev->ip_blocks = topaz_ip_blocks;  in vi_set_ip_blocks()
1329 		adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);  in vi_set_ip_blocks()
1332 		adev->ip_blocks = fiji_ip_blocks;  in vi_set_ip_blocks()
1333 		adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);  in vi_set_ip_blocks()
1336 		adev->ip_blocks = tonga_ip_blocks;  in vi_set_ip_blocks()
1337 		adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);  in vi_set_ip_blocks()
1341 		adev->ip_blocks = cz_ip_blocks;  in vi_set_ip_blocks()
1342 		adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);  in vi_set_ip_blocks()
1356 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)  in vi_get_rev_id()  argument
1358 	if (adev->asic_type == CHIP_TOPAZ)  in vi_get_rev_id()
1361 	else if (adev->flags & AMD_IS_APU)  in vi_get_rev_id()
1387 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_early_init()  local
1389 	if (adev->flags & AMD_IS_APU) {  in vi_common_early_init()
1390 		adev->smc_rreg = &cz_smc_rreg;  in vi_common_early_init()
1391 		adev->smc_wreg = &cz_smc_wreg;  in vi_common_early_init()
1393 		adev->smc_rreg = &vi_smc_rreg;  in vi_common_early_init()
1394 		adev->smc_wreg = &vi_smc_wreg;  in vi_common_early_init()
1396 	adev->pcie_rreg = &vi_pcie_rreg;  in vi_common_early_init()
1397 	adev->pcie_wreg = &vi_pcie_wreg;  in vi_common_early_init()
1398 	adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;  in vi_common_early_init()
1399 	adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;  in vi_common_early_init()
1400 	adev->didt_rreg = &vi_didt_rreg;  in vi_common_early_init()
1401 	adev->didt_wreg = &vi_didt_wreg;  in vi_common_early_init()
1403 	adev->asic_funcs = &vi_asic_funcs;  in vi_common_early_init()
1405 	if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&  in vi_common_early_init()
1409 	adev->rev_id = vi_get_rev_id(adev);  in vi_common_early_init()
1410 	adev->external_rev_id = 0xFF;  in vi_common_early_init()
1411 	switch (adev->asic_type) {  in vi_common_early_init()
1413 		adev->has_uvd = false;  in vi_common_early_init()
1414 		adev->cg_flags = 0;  in vi_common_early_init()
1415 		adev->pg_flags = 0;  in vi_common_early_init()
1416 		adev->external_rev_id = 0x1;  in vi_common_early_init()
1419 		adev->has_uvd = true;  in vi_common_early_init()
1420 		adev->cg_flags = 0;  in vi_common_early_init()
1421 		adev->pg_flags = 0;  in vi_common_early_init()
1422 		adev->external_rev_id = adev->rev_id + 0x3c;  in vi_common_early_init()
1425 		adev->has_uvd = true;  in vi_common_early_init()
1426 		adev->cg_flags = 0;  in vi_common_early_init()
1427 		adev->pg_flags = 0;  in vi_common_early_init()
1428 		adev->external_rev_id = adev->rev_id + 0x14;  in vi_common_early_init()
1432 		adev->has_uvd = true;  in vi_common_early_init()
1433 		adev->cg_flags = 0;  in vi_common_early_init()
1435 		adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE;  in vi_common_early_init()
1436 		adev->external_rev_id = adev->rev_id + 0x1;  in vi_common_early_init()
1444 		adev->firmware.smu_load = true;  in vi_common_early_init()
1461 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_hw_init()  local
1464 	vi_init_golden_registers(adev);  in vi_common_hw_init()
1466 	vi_pcie_gen3_enable(adev);  in vi_common_hw_init()
1468 	vi_program_aspm(adev);  in vi_common_hw_init()
1470 	vi_enable_doorbell_aperture(adev, true);  in vi_common_hw_init()
1477 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_hw_fini()  local
1480 	vi_enable_doorbell_aperture(adev, false);  in vi_common_hw_fini()
1487 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_suspend()  local
1489 	return vi_common_hw_fini(adev);  in vi_common_suspend()
1494 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vi_common_resume()  local
1496 	return vi_common_hw_init(adev);  in vi_common_resume()