85 	WREG32(mmPCIE_INDEX, reg);  in vi_pcie_rreg()
97 	WREG32(mmPCIE_INDEX, reg);  in vi_pcie_wreg()
99 	WREG32(mmPCIE_DATA, v);  in vi_pcie_wreg()
110 	WREG32(mmSMC_IND_INDEX_0, (reg));  in vi_smc_rreg()
121 	WREG32(mmSMC_IND_INDEX_0, (reg));  in vi_smc_wreg()
122 	WREG32(mmSMC_IND_DATA_0, (v));  in vi_smc_wreg()
136 	WREG32(mmMP0PUB_IND_INDEX, (reg));  in cz_smc_rreg()
147 	WREG32(mmMP0PUB_IND_INDEX, (reg));  in cz_smc_wreg()
148 	WREG32(mmMP0PUB_IND_DATA, (v));  in cz_smc_wreg()
158 	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));  in vi_uvd_ctx_rreg()
169 	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));  in vi_uvd_ctx_wreg()
170 	WREG32(mmUVD_CTX_DATA, (v));  in vi_uvd_ctx_wreg()
180 	WREG32(mmDIDT_IND_INDEX, (reg));  in vi_didt_rreg()
191 	WREG32(mmDIDT_IND_INDEX, (reg));  in vi_didt_wreg()
192 	WREG32(mmDIDT_IND_DATA, (v));  in vi_didt_wreg()
328 	WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);  in vi_srbm_select()
354 	WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));  in vi_read_disabled_bios()
357 		WREG32(mmD1VGA_CONTROL,  in vi_read_disabled_bios()
360 		WREG32(mmD2VGA_CONTROL,  in vi_read_disabled_bios()
363 		WREG32(mmVGA_RENDER_CONTROL,  in vi_read_disabled_bios()
371 	WREG32(mmBUS_CNTL, bus_cntl);  in vi_read_disabled_bios()
373 		WREG32(mmD1VGA_CONTROL, d1vga_control);  in vi_read_disabled_bios()
374 		WREG32(mmD2VGA_CONTROL, d2vga_control);  in vi_read_disabled_bios()
375 		WREG32(mmVGA_RENDER_CONTROL, vga_render_control);  in vi_read_disabled_bios()
725 	WREG32(mmCP_ME_CNTL, tmp);  in vi_gpu_soft_reset()
731 	WREG32(mmCP_MEC_CNTL, tmp);  in vi_gpu_soft_reset()
737 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in vi_gpu_soft_reset()
743 		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in vi_gpu_soft_reset()
819 		WREG32(mmGRBM_SOFT_RESET, tmp);  in vi_gpu_soft_reset()
825 		WREG32(mmGRBM_SOFT_RESET, tmp);  in vi_gpu_soft_reset()
833 		WREG32(mmSRBM_SOFT_RESET, tmp);  in vi_gpu_soft_reset()
839 		WREG32(mmSRBM_SOFT_RESET, tmp);  in vi_gpu_soft_reset()
868 	WREG32(mmCP_ME_CNTL, tmp);  in vi_gpu_pci_config_reset()
874 	WREG32(mmCP_MEC_CNTL, tmp);  in vi_gpu_pci_config_reset()
877 	WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |  in vi_gpu_pci_config_reset()
881 	WREG32(mmCP_MEC_CNTL,  in vi_gpu_pci_config_reset()
887 	WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in vi_gpu_pci_config_reset()
892 	WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in vi_gpu_pci_config_reset()
933 	WREG32(mmBIOS_SCRATCH_3, tmp);  in vi_set_bios_scratch_engine_hung()
1069 	WREG32(mmBIF_DOORBELL_APER_EN, tmp);  in vi_enable_doorbell_aperture()