62 static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring *ring)  in vce_v3_0_ring_get_rptr()  argument
64 	struct amdgpu_device *adev = ring->adev;  in vce_v3_0_ring_get_rptr()
66 	if (ring == &adev->vce.ring[0])  in vce_v3_0_ring_get_rptr()
79 static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring *ring)  in vce_v3_0_ring_get_wptr()  argument
81 	struct amdgpu_device *adev = ring->adev;  in vce_v3_0_ring_get_wptr()
83 	if (ring == &adev->vce.ring[0])  in vce_v3_0_ring_get_wptr()
96 static void vce_v3_0_ring_set_wptr(struct amdgpu_ring *ring)  in vce_v3_0_ring_set_wptr()  argument
98 	struct amdgpu_device *adev = ring->adev;  in vce_v3_0_ring_set_wptr()
100 	if (ring == &adev->vce.ring[0])  in vce_v3_0_ring_set_wptr()
101 		WREG32(mmVCE_RB_WPTR, ring->wptr);  in vce_v3_0_ring_set_wptr()
103 		WREG32(mmVCE_RB_WPTR2, ring->wptr);  in vce_v3_0_ring_set_wptr()
115 	struct amdgpu_ring *ring;  in vce_v3_0_start()  local
187 	ring = &adev->vce.ring[0];  in vce_v3_0_start()
188 	WREG32(mmVCE_RB_RPTR, ring->wptr);  in vce_v3_0_start()
189 	WREG32(mmVCE_RB_WPTR, ring->wptr);  in vce_v3_0_start()
190 	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);  in vce_v3_0_start()
191 	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vce_v3_0_start()
192 	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);  in vce_v3_0_start()
194 	ring = &adev->vce.ring[1];  in vce_v3_0_start()
195 	WREG32(mmVCE_RB_RPTR2, ring->wptr);  in vce_v3_0_start()
196 	WREG32(mmVCE_RB_WPTR2, ring->wptr);  in vce_v3_0_start()
197 	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);  in vce_v3_0_start()
198 	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vce_v3_0_start()
199 	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);  in vce_v3_0_start()
267 	struct amdgpu_ring *ring;  in vce_v3_0_sw_init()  local
284 	ring = &adev->vce.ring[0];  in vce_v3_0_sw_init()
285 	sprintf(ring->name, "vce0");  in vce_v3_0_sw_init()
286 	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,  in vce_v3_0_sw_init()
291 	ring = &adev->vce.ring[1];  in vce_v3_0_sw_init()
292 	sprintf(ring->name, "vce1");  in vce_v3_0_sw_init()
293 	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,  in vce_v3_0_sw_init()
319 	struct amdgpu_ring *ring;  in vce_v3_0_hw_init()  local
327 	ring = &adev->vce.ring[0];  in vce_v3_0_hw_init()
328 	ring->ready = true;  in vce_v3_0_hw_init()
329 	r = amdgpu_ring_test_ring(ring);  in vce_v3_0_hw_init()
331 		ring->ready = false;  in vce_v3_0_hw_init()
335 	ring = &adev->vce.ring[1];  in vce_v3_0_hw_init()
336 	ring->ready = true;  in vce_v3_0_hw_init()
337 	r = amdgpu_ring_test_ring(ring);  in vce_v3_0_hw_init()
339 		ring->ready = false;  in vce_v3_0_hw_init()
595 		amdgpu_fence_process(&adev->vce.ring[0]);  in vce_v3_0_process_interrupt()
598 		amdgpu_fence_process(&adev->vce.ring[1]);  in vce_v3_0_process_interrupt()
666 	adev->vce.ring[0].funcs = &vce_v3_0_ring_funcs;  in vce_v3_0_set_ring_funcs()
667 	adev->vce.ring[1].funcs = &vce_v3_0_ring_funcs;  in vce_v3_0_set_ring_funcs()