51 static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
52 static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
53 static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
64 	struct amdgpu_device *adev = ring->adev;  in vce_v3_0_ring_get_rptr()  local
66 	if (ring == &adev->vce.ring[0])  in vce_v3_0_ring_get_rptr()
81 	struct amdgpu_device *adev = ring->adev;  in vce_v3_0_ring_get_wptr()  local
83 	if (ring == &adev->vce.ring[0])  in vce_v3_0_ring_get_wptr()
98 	struct amdgpu_device *adev = ring->adev;  in vce_v3_0_ring_set_wptr()  local
100 	if (ring == &adev->vce.ring[0])  in vce_v3_0_ring_set_wptr()
113 static int vce_v3_0_start(struct amdgpu_device *adev)  in vce_v3_0_start()  argument
118 	mutex_lock(&adev->grbm_idx_mutex);  in vce_v3_0_start()
121 		if (adev->vce.harvest_config & (1 << idx))  in vce_v3_0_start()
132 		vce_v3_0_mc_resume(adev, idx);  in vce_v3_0_start()
136 		if (adev->asic_type >= CHIP_STONEY)  in vce_v3_0_start()
179 			mutex_unlock(&adev->grbm_idx_mutex);  in vce_v3_0_start()
185 	mutex_unlock(&adev->grbm_idx_mutex);  in vce_v3_0_start()
187 	ring = &adev->vce.ring[0];  in vce_v3_0_start()
194 	ring = &adev->vce.ring[1];  in vce_v3_0_start()
208 static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)  in vce_v3_0_get_harvest_config()  argument
214 	if ((adev->asic_type == CHIP_FIJI) ||  in vce_v3_0_get_harvest_config()
215 	    (adev->asic_type == CHIP_STONEY)){  in vce_v3_0_get_harvest_config()
221 	if (adev->flags & AMD_IS_APU)  in vce_v3_0_get_harvest_config()
249 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vce_v3_0_early_init()  local
251 	adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev);  in vce_v3_0_early_init()
253 	if ((adev->vce.harvest_config &  in vce_v3_0_early_init()
258 	vce_v3_0_set_ring_funcs(adev);  in vce_v3_0_early_init()
259 	vce_v3_0_set_irq_funcs(adev);  in vce_v3_0_early_init()
266 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vce_v3_0_sw_init()  local
271 	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);  in vce_v3_0_sw_init()
275 	r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE +  in vce_v3_0_sw_init()
280 	r = amdgpu_vce_resume(adev);  in vce_v3_0_sw_init()
284 	ring = &adev->vce.ring[0];  in vce_v3_0_sw_init()
286 	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,  in vce_v3_0_sw_init()
287 			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);  in vce_v3_0_sw_init()
291 	ring = &adev->vce.ring[1];  in vce_v3_0_sw_init()
293 	r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,  in vce_v3_0_sw_init()
294 			     &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);  in vce_v3_0_sw_init()
304 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vce_v3_0_sw_fini()  local
306 	r = amdgpu_vce_suspend(adev);  in vce_v3_0_sw_fini()
310 	r = amdgpu_vce_sw_fini(adev);  in vce_v3_0_sw_fini()
321 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vce_v3_0_hw_init()  local
323 	r = vce_v3_0_start(adev);  in vce_v3_0_hw_init()
327 	ring = &adev->vce.ring[0];  in vce_v3_0_hw_init()
335 	ring = &adev->vce.ring[1];  in vce_v3_0_hw_init()
356 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vce_v3_0_suspend()  local
358 	r = vce_v3_0_hw_fini(adev);  in vce_v3_0_suspend()
362 	r = amdgpu_vce_suspend(adev);  in vce_v3_0_suspend()
372 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vce_v3_0_resume()  local
374 	r = amdgpu_vce_resume(adev);  in vce_v3_0_resume()
378 	r = vce_v3_0_hw_init(adev);  in vce_v3_0_resume()
385 static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx)  in vce_v3_0_mc_resume()  argument
399 	if (adev->asic_type >= CHIP_STONEY) {  in vce_v3_0_mc_resume()
400 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
401 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
402 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
404 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
438 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vce_v3_0_is_idle()  local
443 		if (adev->vce.harvest_config & (1 << idx))  in vce_v3_0_is_idle()
458 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vce_v3_0_wait_for_idle()  local
463 		if (adev->vce.harvest_config & (1 << idx))  in vce_v3_0_wait_for_idle()
472 	for (i = 0; i < adev->usec_timeout; i++) {  in vce_v3_0_wait_for_idle()
481 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vce_v3_0_soft_reset()  local
486 		if (adev->vce.harvest_config & (1 << idx))  in vce_v3_0_soft_reset()
499 	return vce_v3_0_start(adev);  in vce_v3_0_soft_reset()
504 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vce_v3_0_print_status()  local
506 	dev_info(adev->dev, "VCE 3.0 registers\n");  in vce_v3_0_print_status()
507 	dev_info(adev->dev, "  VCE_STATUS=0x%08X\n",  in vce_v3_0_print_status()
509 	dev_info(adev->dev, "  VCE_VCPU_CNTL=0x%08X\n",  in vce_v3_0_print_status()
511 	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET0=0x%08X\n",  in vce_v3_0_print_status()
513 	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE0=0x%08X\n",  in vce_v3_0_print_status()
515 	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET1=0x%08X\n",  in vce_v3_0_print_status()
517 	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE1=0x%08X\n",  in vce_v3_0_print_status()
519 	dev_info(adev->dev, "  VCE_VCPU_CACHE_OFFSET2=0x%08X\n",  in vce_v3_0_print_status()
521 	dev_info(adev->dev, "  VCE_VCPU_CACHE_SIZE2=0x%08X\n",  in vce_v3_0_print_status()
523 	dev_info(adev->dev, "  VCE_SOFT_RESET=0x%08X\n",  in vce_v3_0_print_status()
525 	dev_info(adev->dev, "  VCE_RB_BASE_LO2=0x%08X\n",  in vce_v3_0_print_status()
527 	dev_info(adev->dev, "  VCE_RB_BASE_HI2=0x%08X\n",  in vce_v3_0_print_status()
529 	dev_info(adev->dev, "  VCE_RB_SIZE2=0x%08X\n",  in vce_v3_0_print_status()
531 	dev_info(adev->dev, "  VCE_RB_RPTR2=0x%08X\n",  in vce_v3_0_print_status()
533 	dev_info(adev->dev, "  VCE_RB_WPTR2=0x%08X\n",  in vce_v3_0_print_status()
535 	dev_info(adev->dev, "  VCE_RB_BASE_LO=0x%08X\n",  in vce_v3_0_print_status()
537 	dev_info(adev->dev, "  VCE_RB_BASE_HI=0x%08X\n",  in vce_v3_0_print_status()
539 	dev_info(adev->dev, "  VCE_RB_SIZE=0x%08X\n",  in vce_v3_0_print_status()
541 	dev_info(adev->dev, "  VCE_RB_RPTR=0x%08X\n",  in vce_v3_0_print_status()
543 	dev_info(adev->dev, "  VCE_RB_WPTR=0x%08X\n",  in vce_v3_0_print_status()
545 	dev_info(adev->dev, "  VCE_CLOCK_GATING_A=0x%08X\n",  in vce_v3_0_print_status()
547 	dev_info(adev->dev, "  VCE_CLOCK_GATING_B=0x%08X\n",  in vce_v3_0_print_status()
549 	dev_info(adev->dev, "  VCE_UENC_CLOCK_GATING=0x%08X\n",  in vce_v3_0_print_status()
551 	dev_info(adev->dev, "  VCE_UENC_REG_CLOCK_GATING=0x%08X\n",  in vce_v3_0_print_status()
553 	dev_info(adev->dev, "  VCE_SYS_INT_EN=0x%08X\n",  in vce_v3_0_print_status()
555 	dev_info(adev->dev, "  VCE_LMI_CTRL2=0x%08X\n",  in vce_v3_0_print_status()
557 	dev_info(adev->dev, "  VCE_LMI_CTRL=0x%08X\n",  in vce_v3_0_print_status()
559 	dev_info(adev->dev, "  VCE_LMI_VM_CTRL=0x%08X\n",  in vce_v3_0_print_status()
561 	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL=0x%08X\n",  in vce_v3_0_print_status()
563 	dev_info(adev->dev, "  VCE_LMI_SWAP_CNTL1=0x%08X\n",  in vce_v3_0_print_status()
565 	dev_info(adev->dev, "  VCE_LMI_CACHE_CTRL=0x%08X\n",  in vce_v3_0_print_status()
569 static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,  in vce_v3_0_set_interrupt_state()  argument
583 static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,  in vce_v3_0_process_interrupt()  argument
595 		amdgpu_fence_process(&adev->vce.ring[0]);  in vce_v3_0_process_interrupt()
598 		amdgpu_fence_process(&adev->vce.ring[1]);  in vce_v3_0_process_interrupt()
625 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in vce_v3_0_set_powergating_state()  local
631 		return vce_v3_0_start(adev);  in vce_v3_0_set_powergating_state()
664 static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)  in vce_v3_0_set_ring_funcs()  argument
666 	adev->vce.ring[0].funcs = &vce_v3_0_ring_funcs;  in vce_v3_0_set_ring_funcs()
667 	adev->vce.ring[1].funcs = &vce_v3_0_ring_funcs;  in vce_v3_0_set_ring_funcs()
675 static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev)  in vce_v3_0_set_irq_funcs()  argument
677 	adev->vce.irq.num_types = 1;  in vce_v3_0_set_irq_funcs()
678 	adev->vce.irq.funcs = &vce_v3_0_irq_funcs;  in vce_v3_0_set_irq_funcs()