101 		WREG32(mmVCE_RB_WPTR, ring->wptr);  in vce_v3_0_ring_set_wptr()
103 		WREG32(mmVCE_RB_WPTR2, ring->wptr);  in vce_v3_0_ring_set_wptr()
188 	WREG32(mmVCE_RB_RPTR, ring->wptr);  in vce_v3_0_start()
189 	WREG32(mmVCE_RB_WPTR, ring->wptr);  in vce_v3_0_start()
190 	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);  in vce_v3_0_start()
191 	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vce_v3_0_start()
192 	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);  in vce_v3_0_start()
195 	WREG32(mmVCE_RB_RPTR2, ring->wptr);  in vce_v3_0_start()
196 	WREG32(mmVCE_RB_WPTR2, ring->wptr);  in vce_v3_0_start()
197 	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);  in vce_v3_0_start()
198 	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vce_v3_0_start()
199 	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);  in vce_v3_0_start()
392 	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);  in vce_v3_0_mc_resume()
394 	WREG32(mmVCE_LMI_CTRL, 0x00398000);  in vce_v3_0_mc_resume()
396 	WREG32(mmVCE_LMI_SWAP_CNTL, 0);  in vce_v3_0_mc_resume()
397 	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);  in vce_v3_0_mc_resume()
398 	WREG32(mmVCE_LMI_VM_CTRL, 0);  in vce_v3_0_mc_resume()
400 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
401 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
402 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
404 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));  in vce_v3_0_mc_resume()
407 	WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);  in vce_v3_0_mc_resume()
408 	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);  in vce_v3_0_mc_resume()
413 		WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);  in vce_v3_0_mc_resume()
414 		WREG32(mmVCE_VCPU_CACHE_SIZE1, size);  in vce_v3_0_mc_resume()
417 		WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);  in vce_v3_0_mc_resume()
418 		WREG32(mmVCE_VCPU_CACHE_SIZE2, size);  in vce_v3_0_mc_resume()
422 		WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);  in vce_v3_0_mc_resume()
423 		WREG32(mmVCE_VCPU_CACHE_SIZE1, size);  in vce_v3_0_mc_resume()
426 		WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff);  in vce_v3_0_mc_resume()
427 		WREG32(mmVCE_VCPU_CACHE_SIZE2, size);  in vce_v3_0_mc_resume()