305 	u32 tmp;  in vce_v2_0_set_sw_cg()  local
308 		tmp = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v2_0_set_sw_cg()
309 		tmp |= 0xe70000;  in vce_v2_0_set_sw_cg()
310 		WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_set_sw_cg()
312 		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v2_0_set_sw_cg()
313 		tmp |= 0xff000000;  in vce_v2_0_set_sw_cg()
314 		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
316 		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v2_0_set_sw_cg()
317 		tmp &= ~0x3fc;  in vce_v2_0_set_sw_cg()
318 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
322 		tmp = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v2_0_set_sw_cg()
323 		tmp |= 0xe7;  in vce_v2_0_set_sw_cg()
324 		tmp &= ~0xe70000;  in vce_v2_0_set_sw_cg()
325 		WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_set_sw_cg()
327 		tmp = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v2_0_set_sw_cg()
328 		tmp |= 0x1fe000;  in vce_v2_0_set_sw_cg()
329 		tmp &= ~0xff000000;  in vce_v2_0_set_sw_cg()
330 		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
332 		tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v2_0_set_sw_cg()
333 		tmp |= 0x3fc;  in vce_v2_0_set_sw_cg()
334 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
340 	u32 orig, tmp;  in vce_v2_0_set_dyn_cg()  local
342 	tmp = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v2_0_set_dyn_cg()
343 	tmp &= ~0x00060006;  in vce_v2_0_set_dyn_cg()
345 		tmp |= 0xe10000;  in vce_v2_0_set_dyn_cg()
347 		tmp |= 0xe1;  in vce_v2_0_set_dyn_cg()
348 		tmp &= ~0xe10000;  in vce_v2_0_set_dyn_cg()
350 	WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_set_dyn_cg()
352 	orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v2_0_set_dyn_cg()
353 	tmp &= ~0x1fe000;  in vce_v2_0_set_dyn_cg()
354 	tmp &= ~0xff000000;  in vce_v2_0_set_dyn_cg()
355 	if (tmp != orig)  in vce_v2_0_set_dyn_cg()
356 		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_set_dyn_cg()
358 	orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);  in vce_v2_0_set_dyn_cg()
359 	tmp &= ~0x3fc;  in vce_v2_0_set_dyn_cg()
360 	if (tmp != orig)  in vce_v2_0_set_dyn_cg()
361 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v2_0_set_dyn_cg()
393 	u32 tmp;  in vce_v2_0_init_cg()  local
395 	tmp = RREG32(mmVCE_CLOCK_GATING_A);  in vce_v2_0_init_cg()
396 	tmp &= ~0xfff;  in vce_v2_0_init_cg()
397 	tmp |= ((0 << 0) | (4 << 4));  in vce_v2_0_init_cg()
398 	tmp |= 0x40000;  in vce_v2_0_init_cg()
399 	WREG32(mmVCE_CLOCK_GATING_A, tmp);  in vce_v2_0_init_cg()
401 	tmp = RREG32(mmVCE_UENC_CLOCK_GATING);  in vce_v2_0_init_cg()
402 	tmp &= ~0xfff;  in vce_v2_0_init_cg()
403 	tmp |= ((0 << 0) | (4 << 4));  in vce_v2_0_init_cg()
404 	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_init_cg()
406 	tmp = RREG32(mmVCE_CLOCK_GATING_B);  in vce_v2_0_init_cg()
407 	tmp |= 0x10;  in vce_v2_0_init_cg()
408 	tmp &= ~0x100000;  in vce_v2_0_init_cg()
409 	WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_init_cg()