94 		WREG32(mmVCE_RB_WPTR, ring->wptr);  in vce_v2_0_ring_set_wptr()
96 		WREG32(mmVCE_RB_WPTR2, ring->wptr);  in vce_v2_0_ring_set_wptr()
117 	WREG32(mmVCE_RB_RPTR, ring->wptr);  in vce_v2_0_start()
118 	WREG32(mmVCE_RB_WPTR, ring->wptr);  in vce_v2_0_start()
119 	WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);  in vce_v2_0_start()
120 	WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));  in vce_v2_0_start()
121 	WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);  in vce_v2_0_start()
124 	WREG32(mmVCE_RB_RPTR2, ring->wptr);  in vce_v2_0_start()
125 	WREG32(mmVCE_RB_WPTR2, ring->wptr);  in vce_v2_0_start()
126 	WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);  in vce_v2_0_start()
127 	WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));  in vce_v2_0_start()
128 	WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);  in vce_v2_0_start()
310 		WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_set_sw_cg()
314 		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
318 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
320 		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);  in vce_v2_0_set_sw_cg()
325 		WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_set_sw_cg()
330 		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
334 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v2_0_set_sw_cg()
350 	WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_set_dyn_cg()
356 		WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_set_dyn_cg()
361 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);  in vce_v2_0_set_dyn_cg()
364 		WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);  in vce_v2_0_set_dyn_cg()
369 	WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);  in vce_v2_0_disable_cg()
399 	WREG32(mmVCE_CLOCK_GATING_A, tmp);  in vce_v2_0_init_cg()
404 	WREG32(mmVCE_UENC_CLOCK_GATING, tmp);  in vce_v2_0_init_cg()
409 	WREG32(mmVCE_CLOCK_GATING_B, tmp);  in vce_v2_0_init_cg()
420 	WREG32(mmVCE_CLOCK_GATING_B, 0xf7);  in vce_v2_0_mc_resume()
422 	WREG32(mmVCE_LMI_CTRL, 0x00398000);  in vce_v2_0_mc_resume()
424 	WREG32(mmVCE_LMI_SWAP_CNTL, 0);  in vce_v2_0_mc_resume()
425 	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);  in vce_v2_0_mc_resume()
426 	WREG32(mmVCE_LMI_VM_CTRL, 0);  in vce_v2_0_mc_resume()
430 	WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);  in vce_v2_0_mc_resume()
431 	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);  in vce_v2_0_mc_resume()
435 	WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);  in vce_v2_0_mc_resume()
436 	WREG32(mmVCE_VCPU_CACHE_SIZE1, size);  in vce_v2_0_mc_resume()
440 	WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);  in vce_v2_0_mc_resume()
441 	WREG32(mmVCE_VCPU_CACHE_SIZE2, size);  in vce_v2_0_mc_resume()