Lines Matching refs:adev
35 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
36 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
37 static int uvd_v6_0_start(struct amdgpu_device *adev);
38 static void uvd_v6_0_stop(struct amdgpu_device *adev);
49 struct amdgpu_device *adev = ring->adev; in uvd_v6_0_ring_get_rptr() local
63 struct amdgpu_device *adev = ring->adev; in uvd_v6_0_ring_get_wptr() local
77 struct amdgpu_device *adev = ring->adev; in uvd_v6_0_ring_set_wptr() local
84 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_early_init() local
86 uvd_v6_0_set_ring_funcs(adev); in uvd_v6_0_early_init()
87 uvd_v6_0_set_irq_funcs(adev); in uvd_v6_0_early_init()
96 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_sw_init() local
99 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); in uvd_v6_0_sw_init()
103 r = amdgpu_uvd_sw_init(adev); in uvd_v6_0_sw_init()
107 r = amdgpu_uvd_resume(adev); in uvd_v6_0_sw_init()
111 ring = &adev->uvd.ring; in uvd_v6_0_sw_init()
113 r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, in uvd_v6_0_sw_init()
114 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); in uvd_v6_0_sw_init()
122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_sw_fini() local
124 r = amdgpu_uvd_suspend(adev); in uvd_v6_0_sw_fini()
128 r = amdgpu_uvd_sw_fini(adev); in uvd_v6_0_sw_fini()
144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_hw_init() local
145 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v6_0_hw_init()
149 r = uvd_v6_0_start(adev); in uvd_v6_0_hw_init()
203 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_hw_fini() local
204 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v6_0_hw_fini()
206 uvd_v6_0_stop(adev); in uvd_v6_0_hw_fini()
215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_suspend() local
218 if (!(adev->flags & AMD_IS_APU)) { in uvd_v6_0_suspend()
219 r = amdgpu_uvd_suspend(adev); in uvd_v6_0_suspend()
223 r = uvd_v6_0_hw_fini(adev); in uvd_v6_0_suspend()
233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_resume() local
236 if (!(adev->flags & AMD_IS_APU)) { in uvd_v6_0_resume()
237 r = amdgpu_uvd_resume(adev); in uvd_v6_0_resume()
241 r = uvd_v6_0_hw_init(adev); in uvd_v6_0_resume()
255 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) in uvd_v6_0_mc_resume() argument
262 lower_32_bits(adev->uvd.gpu_addr)); in uvd_v6_0_mc_resume()
264 upper_32_bits(adev->uvd.gpu_addr)); in uvd_v6_0_mc_resume()
267 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); in uvd_v6_0_mc_resume()
289 static int uvd_v6_0_start(struct amdgpu_device *adev) in uvd_v6_0_start() argument
291 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v6_0_start()
304 uvd_v6_0_mc_resume(adev); in uvd_v6_0_start()
435 static void uvd_v6_0_stop(struct amdgpu_device *adev) in uvd_v6_0_stop() argument
521 struct amdgpu_device *adev = ring->adev; in uvd_v6_0_ring_test_ring() local
536 for (i = 0; i < adev->usec_timeout; i++) { in uvd_v6_0_ring_test_ring()
543 if (i < adev->usec_timeout) { in uvd_v6_0_ring_test_ring()
610 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_is_idle() local
618 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_wait_for_idle() local
620 for (i = 0; i < adev->usec_timeout; i++) { in uvd_v6_0_wait_for_idle()
629 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_soft_reset() local
631 uvd_v6_0_stop(adev); in uvd_v6_0_soft_reset()
637 return uvd_v6_0_start(adev); in uvd_v6_0_soft_reset()
642 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_print_status() local
643 dev_info(adev->dev, "UVD 6.0 registers\n"); in uvd_v6_0_print_status()
644 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", in uvd_v6_0_print_status()
646 dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", in uvd_v6_0_print_status()
648 dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", in uvd_v6_0_print_status()
650 dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", in uvd_v6_0_print_status()
652 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", in uvd_v6_0_print_status()
654 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", in uvd_v6_0_print_status()
656 dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", in uvd_v6_0_print_status()
658 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", in uvd_v6_0_print_status()
660 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", in uvd_v6_0_print_status()
662 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", in uvd_v6_0_print_status()
664 dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", in uvd_v6_0_print_status()
666 dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", in uvd_v6_0_print_status()
668 dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", in uvd_v6_0_print_status()
670 dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", in uvd_v6_0_print_status()
672 dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", in uvd_v6_0_print_status()
674 dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", in uvd_v6_0_print_status()
676 dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", in uvd_v6_0_print_status()
678 dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", in uvd_v6_0_print_status()
680 dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", in uvd_v6_0_print_status()
682 dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", in uvd_v6_0_print_status()
684 dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", in uvd_v6_0_print_status()
686 dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", in uvd_v6_0_print_status()
688 dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", in uvd_v6_0_print_status()
690 dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", in uvd_v6_0_print_status()
692 dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", in uvd_v6_0_print_status()
694 dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", in uvd_v6_0_print_status()
696 dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", in uvd_v6_0_print_status()
698 dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", in uvd_v6_0_print_status()
700 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", in uvd_v6_0_print_status()
702 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", in uvd_v6_0_print_status()
704 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", in uvd_v6_0_print_status()
706 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", in uvd_v6_0_print_status()
708 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", in uvd_v6_0_print_status()
710 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", in uvd_v6_0_print_status()
712 dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", in uvd_v6_0_print_status()
714 dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", in uvd_v6_0_print_status()
716 dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", in uvd_v6_0_print_status()
718 dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", in uvd_v6_0_print_status()
720 dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", in uvd_v6_0_print_status()
722 dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", in uvd_v6_0_print_status()
724 dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", in uvd_v6_0_print_status()
726 dev_info(adev->dev, " UVD_STATUS=0x%08X\n", in uvd_v6_0_print_status()
728 dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", in uvd_v6_0_print_status()
730 dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", in uvd_v6_0_print_status()
732 dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", in uvd_v6_0_print_status()
734 dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", in uvd_v6_0_print_status()
736 dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", in uvd_v6_0_print_status()
740 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, in uvd_v6_0_set_interrupt_state() argument
749 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, in uvd_v6_0_process_interrupt() argument
754 amdgpu_fence_process(&adev->uvd.ring); in uvd_v6_0_process_interrupt()
774 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in uvd_v6_0_set_powergating_state() local
777 uvd_v6_0_stop(adev); in uvd_v6_0_set_powergating_state()
780 return uvd_v6_0_start(adev); in uvd_v6_0_set_powergating_state()
814 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) in uvd_v6_0_set_ring_funcs() argument
816 adev->uvd.ring.funcs = &uvd_v6_0_ring_funcs; in uvd_v6_0_set_ring_funcs()
824 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev) in uvd_v6_0_set_irq_funcs() argument
826 adev->uvd.irq.num_types = 1; in uvd_v6_0_set_irq_funcs()
827 adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs; in uvd_v6_0_set_irq_funcs()