79 	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);  in uvd_v6_0_ring_set_wptr()
261 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,  in uvd_v6_0_mc_resume()
263 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,  in uvd_v6_0_mc_resume()
268 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);  in uvd_v6_0_mc_resume()
269 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);  in uvd_v6_0_mc_resume()
273 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);  in uvd_v6_0_mc_resume()
274 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);  in uvd_v6_0_mc_resume()
278 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);  in uvd_v6_0_mc_resume()
279 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);  in uvd_v6_0_mc_resume()
307 	WREG32(mmUVD_CGC_GATE, 0);  in uvd_v6_0_start()
317 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |  in uvd_v6_0_start()
329 	WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |  in uvd_v6_0_start()
337 	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);  in uvd_v6_0_start()
338 	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);  in uvd_v6_0_start()
340 	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);  in uvd_v6_0_start()
341 	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);  in uvd_v6_0_start()
342 	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);  in uvd_v6_0_start()
343 	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);  in uvd_v6_0_start()
344 	WREG32(mmUVD_MPC_SET_ALU, 0);  in uvd_v6_0_start()
345 	WREG32(mmUVD_MPC_SET_MUX, 0x88);  in uvd_v6_0_start()
348 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);  in uvd_v6_0_start()
352 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);  in uvd_v6_0_start()
358 	WREG32(mmUVD_SOFT_RESET, 0);  in uvd_v6_0_start()
403 	WREG32(mmUVD_RBC_RB_CNTL, tmp);  in uvd_v6_0_start()
406 	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);  in uvd_v6_0_start()
409 	WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));  in uvd_v6_0_start()
412 	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,  in uvd_v6_0_start()
414 	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,  in uvd_v6_0_start()
418 	WREG32(mmUVD_RBC_RB_RPTR, 0);  in uvd_v6_0_start()
421 	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);  in uvd_v6_0_start()
438 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);  in uvd_v6_0_stop()
445 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);  in uvd_v6_0_stop()
449 	WREG32(mmUVD_VCPU_CNTL, 0x0);  in uvd_v6_0_stop()
526 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);  in uvd_v6_0_ring_test_ring()