Lines Matching refs:ring
47 static uint32_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) in uvd_v5_0_ring_get_rptr() argument
49 struct amdgpu_device *adev = ring->adev; in uvd_v5_0_ring_get_rptr()
61 static uint32_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) in uvd_v5_0_ring_get_wptr() argument
63 struct amdgpu_device *adev = ring->adev; in uvd_v5_0_ring_get_wptr()
75 static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) in uvd_v5_0_ring_set_wptr() argument
77 struct amdgpu_device *adev = ring->adev; in uvd_v5_0_ring_set_wptr()
79 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); in uvd_v5_0_ring_set_wptr()
94 struct amdgpu_ring *ring; in uvd_v5_0_sw_init() local
111 ring = &adev->uvd.ring; in uvd_v5_0_sw_init()
112 sprintf(ring->name, "uvd"); in uvd_v5_0_sw_init()
113 r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, in uvd_v5_0_sw_init()
145 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v5_0_hw_init() local
156 ring->ready = true; in uvd_v5_0_hw_init()
157 r = amdgpu_ring_test_ring(ring); in uvd_v5_0_hw_init()
159 ring->ready = false; in uvd_v5_0_hw_init()
163 r = amdgpu_ring_lock(ring, 10); in uvd_v5_0_hw_init()
170 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
171 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
174 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
175 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
178 amdgpu_ring_write(ring, tmp); in uvd_v5_0_hw_init()
179 amdgpu_ring_write(ring, 0xFFFFF); in uvd_v5_0_hw_init()
182 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init()
183 amdgpu_ring_write(ring, 0x8); in uvd_v5_0_hw_init()
185 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
186 amdgpu_ring_write(ring, 3); in uvd_v5_0_hw_init()
188 amdgpu_ring_unlock_commit(ring); in uvd_v5_0_hw_init()
210 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v5_0_hw_fini() local
213 ring->ready = false; in uvd_v5_0_hw_fini()
293 struct amdgpu_ring *ring = &adev->uvd.ring; in uvd_v5_0_start() local
394 rb_bufsz = order_base_2(ring->ring_size); in uvd_v5_0_start()
409 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); in uvd_v5_0_start()
413 lower_32_bits(ring->gpu_addr)); in uvd_v5_0_start()
415 upper_32_bits(ring->gpu_addr)); in uvd_v5_0_start()
420 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); in uvd_v5_0_start()
421 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); in uvd_v5_0_start()
463 static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, in uvd_v5_0_ring_emit_fence() argument
468 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_emit_fence()
469 amdgpu_ring_write(ring, seq); in uvd_v5_0_ring_emit_fence()
470 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v5_0_ring_emit_fence()
471 amdgpu_ring_write(ring, addr & 0xffffffff); in uvd_v5_0_ring_emit_fence()
472 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v5_0_ring_emit_fence()
473 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); in uvd_v5_0_ring_emit_fence()
474 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v5_0_ring_emit_fence()
475 amdgpu_ring_write(ring, 0); in uvd_v5_0_ring_emit_fence()
477 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v5_0_ring_emit_fence()
478 amdgpu_ring_write(ring, 0); in uvd_v5_0_ring_emit_fence()
479 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v5_0_ring_emit_fence()
480 amdgpu_ring_write(ring, 0); in uvd_v5_0_ring_emit_fence()
481 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v5_0_ring_emit_fence()
482 amdgpu_ring_write(ring, 2); in uvd_v5_0_ring_emit_fence()
494 static bool uvd_v5_0_ring_emit_semaphore(struct amdgpu_ring *ring, in uvd_v5_0_ring_emit_semaphore() argument
500 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0)); in uvd_v5_0_ring_emit_semaphore()
501 amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); in uvd_v5_0_ring_emit_semaphore()
503 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0)); in uvd_v5_0_ring_emit_semaphore()
504 amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); in uvd_v5_0_ring_emit_semaphore()
506 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0)); in uvd_v5_0_ring_emit_semaphore()
507 amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); in uvd_v5_0_ring_emit_semaphore()
519 static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) in uvd_v5_0_ring_test_ring() argument
521 struct amdgpu_device *adev = ring->adev; in uvd_v5_0_ring_test_ring()
527 r = amdgpu_ring_lock(ring, 3); in uvd_v5_0_ring_test_ring()
530 ring->idx, r); in uvd_v5_0_ring_test_ring()
533 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_test_ring()
534 amdgpu_ring_write(ring, 0xDEADBEEF); in uvd_v5_0_ring_test_ring()
535 amdgpu_ring_unlock_commit(ring); in uvd_v5_0_ring_test_ring()
545 ring->idx, i); in uvd_v5_0_ring_test_ring()
548 ring->idx, tmp); in uvd_v5_0_ring_test_ring()
562 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, in uvd_v5_0_ring_emit_ib() argument
565 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); in uvd_v5_0_ring_emit_ib()
566 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v5_0_ring_emit_ib()
567 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); in uvd_v5_0_ring_emit_ib()
568 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in uvd_v5_0_ring_emit_ib()
569 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); in uvd_v5_0_ring_emit_ib()
570 amdgpu_ring_write(ring, ib->length_dw); in uvd_v5_0_ring_emit_ib()
580 static int uvd_v5_0_ring_test_ib(struct amdgpu_ring *ring) in uvd_v5_0_ring_test_ib() argument
582 struct amdgpu_device *adev = ring->adev; in uvd_v5_0_ring_test_ib()
592 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); in uvd_v5_0_ring_test_ib()
598 r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence); in uvd_v5_0_ring_test_ib()
609 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); in uvd_v5_0_ring_test_ib()
770 amdgpu_fence_process(&adev->uvd.ring); in uvd_v5_0_process_interrupt()
832 adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs; in uvd_v5_0_set_ring_funcs()