96 	int r;  in uvd_v5_0_sw_init()  local
99 	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);  in uvd_v5_0_sw_init()
100 	if (r)  in uvd_v5_0_sw_init()
101 		return r;  in uvd_v5_0_sw_init()
103 	r = amdgpu_uvd_sw_init(adev);  in uvd_v5_0_sw_init()
104 	if (r)  in uvd_v5_0_sw_init()
105 		return r;  in uvd_v5_0_sw_init()
107 	r = amdgpu_uvd_resume(adev);  in uvd_v5_0_sw_init()
108 	if (r)  in uvd_v5_0_sw_init()
109 		return r;  in uvd_v5_0_sw_init()
113 	r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,  in uvd_v5_0_sw_init()
116 	return r;  in uvd_v5_0_sw_init()
121 	int r;  in uvd_v5_0_sw_fini()  local
124 	r = amdgpu_uvd_suspend(adev);  in uvd_v5_0_sw_fini()
125 	if (r)  in uvd_v5_0_sw_fini()
126 		return r;  in uvd_v5_0_sw_fini()
128 	r = amdgpu_uvd_sw_fini(adev);  in uvd_v5_0_sw_fini()
129 	if (r)  in uvd_v5_0_sw_fini()
130 		return r;  in uvd_v5_0_sw_fini()
132 	return r;  in uvd_v5_0_sw_fini()
147 	int r;  in uvd_v5_0_hw_init()  local
152 	r = uvd_v5_0_start(adev);  in uvd_v5_0_hw_init()
153 	if (r)  in uvd_v5_0_hw_init()
157 	r = amdgpu_ring_test_ring(ring);  in uvd_v5_0_hw_init()
158 	if (r) {  in uvd_v5_0_hw_init()
163 	r = amdgpu_ring_lock(ring, 10);  in uvd_v5_0_hw_init()
164 	if (r) {  in uvd_v5_0_hw_init()
165 		DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);  in uvd_v5_0_hw_init()
194 	if (!r)  in uvd_v5_0_hw_init()
197 	return r;  in uvd_v5_0_hw_init()
220 	int r;  in uvd_v5_0_suspend()  local
223 	r = amdgpu_uvd_suspend(adev);  in uvd_v5_0_suspend()
224 	if (r)  in uvd_v5_0_suspend()
225 		return r;  in uvd_v5_0_suspend()
227 	r = uvd_v5_0_hw_fini(adev);  in uvd_v5_0_suspend()
228 	if (r)  in uvd_v5_0_suspend()
229 		return r;  in uvd_v5_0_suspend()
231 	return r;  in uvd_v5_0_suspend()
236 	int r;  in uvd_v5_0_resume()  local
239 	r = amdgpu_uvd_resume(adev);  in uvd_v5_0_resume()
240 	if (r)  in uvd_v5_0_resume()
241 		return r;  in uvd_v5_0_resume()
243 	r = uvd_v5_0_hw_init(adev);  in uvd_v5_0_resume()
244 	if (r)  in uvd_v5_0_resume()
245 		return r;  in uvd_v5_0_resume()
247 	return r;  in uvd_v5_0_resume()
297 	int i, j, r;  in uvd_v5_0_start()  local
371 		r = 0;  in uvd_v5_0_start()
381 		r = -1;  in uvd_v5_0_start()
384 	if (r) {  in uvd_v5_0_start()
386 		return r;  in uvd_v5_0_start()
524 	int r;  in uvd_v5_0_ring_test_ring()  local
527 	r = amdgpu_ring_lock(ring, 3);  in uvd_v5_0_ring_test_ring()
528 	if (r) {  in uvd_v5_0_ring_test_ring()
530 			  ring->idx, r);  in uvd_v5_0_ring_test_ring()
531 		return r;  in uvd_v5_0_ring_test_ring()
549 		r = -EINVAL;  in uvd_v5_0_ring_test_ring()
551 	return r;  in uvd_v5_0_ring_test_ring()
584 	int r;  in uvd_v5_0_ring_test_ib()  local
586 	r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);  in uvd_v5_0_ring_test_ib()
587 	if (r) {  in uvd_v5_0_ring_test_ib()
588 		DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r);  in uvd_v5_0_ring_test_ib()
589 		return r;  in uvd_v5_0_ring_test_ib()
592 	r = amdgpu_uvd_get_create_msg(ring, 1, NULL);  in uvd_v5_0_ring_test_ib()
593 	if (r) {  in uvd_v5_0_ring_test_ib()
594 		DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);  in uvd_v5_0_ring_test_ib()
598 	r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);  in uvd_v5_0_ring_test_ib()
599 	if (r) {  in uvd_v5_0_ring_test_ib()
600 		DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);  in uvd_v5_0_ring_test_ib()
604 	r = fence_wait(fence, false);  in uvd_v5_0_ring_test_ib()
605 	if (r) {  in uvd_v5_0_ring_test_ib()
606 		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);  in uvd_v5_0_ring_test_ib()
613 	return r;  in uvd_v5_0_ring_test_ib()