51 static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)  in uvd_v4_2_ring_get_rptr()  argument
53 	struct amdgpu_device *adev = ring->adev;  in uvd_v4_2_ring_get_rptr()
65 static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)  in uvd_v4_2_ring_get_wptr()  argument
67 	struct amdgpu_device *adev = ring->adev;  in uvd_v4_2_ring_get_wptr()
79 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)  in uvd_v4_2_ring_set_wptr()  argument
81 	struct amdgpu_device *adev = ring->adev;  in uvd_v4_2_ring_set_wptr()
83 	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);  in uvd_v4_2_ring_set_wptr()
98 	struct amdgpu_ring *ring;  in uvd_v4_2_sw_init()  local
115 	ring = &adev->uvd.ring;  in uvd_v4_2_sw_init()
116 	sprintf(ring->name, "uvd");  in uvd_v4_2_sw_init()
117 	r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,  in uvd_v4_2_sw_init()
149 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v4_2_hw_init()  local
160 	ring->ready = true;  in uvd_v4_2_hw_init()
161 	r = amdgpu_ring_test_ring(ring);  in uvd_v4_2_hw_init()
163 		ring->ready = false;  in uvd_v4_2_hw_init()
167 	r = amdgpu_ring_lock(ring, 10);  in uvd_v4_2_hw_init()
174 	amdgpu_ring_write(ring, tmp);  in uvd_v4_2_hw_init()
175 	amdgpu_ring_write(ring, 0xFFFFF);  in uvd_v4_2_hw_init()
178 	amdgpu_ring_write(ring, tmp);  in uvd_v4_2_hw_init()
179 	amdgpu_ring_write(ring, 0xFFFFF);  in uvd_v4_2_hw_init()
182 	amdgpu_ring_write(ring, tmp);  in uvd_v4_2_hw_init()
183 	amdgpu_ring_write(ring, 0xFFFFF);  in uvd_v4_2_hw_init()
186 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));  in uvd_v4_2_hw_init()
187 	amdgpu_ring_write(ring, 0x8);  in uvd_v4_2_hw_init()
189 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));  in uvd_v4_2_hw_init()
190 	amdgpu_ring_write(ring, 3);  in uvd_v4_2_hw_init()
192 	amdgpu_ring_unlock_commit(ring);  in uvd_v4_2_hw_init()
214 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v4_2_hw_fini()  local
217 	ring->ready = false;  in uvd_v4_2_hw_fini()
263 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v4_2_start()  local
364 	WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |  in uvd_v4_2_start()
370 	ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);  in uvd_v4_2_start()
371 	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);  in uvd_v4_2_start()
374 	WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);  in uvd_v4_2_start()
377 	rb_bufsz = order_base_2(ring->ring_size);  in uvd_v4_2_start()
419 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,  in uvd_v4_2_ring_emit_fence()  argument
424 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v4_2_ring_emit_fence()
425 	amdgpu_ring_write(ring, seq);  in uvd_v4_2_ring_emit_fence()
426 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v4_2_ring_emit_fence()
427 	amdgpu_ring_write(ring, addr & 0xffffffff);  in uvd_v4_2_ring_emit_fence()
428 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v4_2_ring_emit_fence()
429 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);  in uvd_v4_2_ring_emit_fence()
430 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v4_2_ring_emit_fence()
431 	amdgpu_ring_write(ring, 0);  in uvd_v4_2_ring_emit_fence()
433 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v4_2_ring_emit_fence()
434 	amdgpu_ring_write(ring, 0);  in uvd_v4_2_ring_emit_fence()
435 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v4_2_ring_emit_fence()
436 	amdgpu_ring_write(ring, 0);  in uvd_v4_2_ring_emit_fence()
437 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v4_2_ring_emit_fence()
438 	amdgpu_ring_write(ring, 2);  in uvd_v4_2_ring_emit_fence()
450 static bool uvd_v4_2_ring_emit_semaphore(struct amdgpu_ring *ring,  in uvd_v4_2_ring_emit_semaphore()  argument
456 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));  in uvd_v4_2_ring_emit_semaphore()
457 	amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF);  in uvd_v4_2_ring_emit_semaphore()
459 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));  in uvd_v4_2_ring_emit_semaphore()
460 	amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF);  in uvd_v4_2_ring_emit_semaphore()
462 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));  in uvd_v4_2_ring_emit_semaphore()
463 	amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));  in uvd_v4_2_ring_emit_semaphore()
475 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)  in uvd_v4_2_ring_test_ring()  argument
477 	struct amdgpu_device *adev = ring->adev;  in uvd_v4_2_ring_test_ring()
483 	r = amdgpu_ring_lock(ring, 3);  in uvd_v4_2_ring_test_ring()
486 			  ring->idx, r);  in uvd_v4_2_ring_test_ring()
489 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v4_2_ring_test_ring()
490 	amdgpu_ring_write(ring, 0xDEADBEEF);  in uvd_v4_2_ring_test_ring()
491 	amdgpu_ring_unlock_commit(ring);  in uvd_v4_2_ring_test_ring()
501 			 ring->idx, i);  in uvd_v4_2_ring_test_ring()
504 			  ring->idx, tmp);  in uvd_v4_2_ring_test_ring()
518 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,  in uvd_v4_2_ring_emit_ib()  argument
521 	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));  in uvd_v4_2_ring_emit_ib()
522 	amdgpu_ring_write(ring, ib->gpu_addr);  in uvd_v4_2_ring_emit_ib()
523 	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));  in uvd_v4_2_ring_emit_ib()
524 	amdgpu_ring_write(ring, ib->length_dw);  in uvd_v4_2_ring_emit_ib()
534 static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring)  in uvd_v4_2_ring_test_ib()  argument
536 	struct amdgpu_device *adev = ring->adev;  in uvd_v4_2_ring_test_ib()
546 	r = amdgpu_uvd_get_create_msg(ring, 1, NULL);  in uvd_v4_2_ring_test_ib()
552 	r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);  in uvd_v4_2_ring_test_ib()
563 	DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);  in uvd_v4_2_ring_test_ib()
823 	amdgpu_fence_process(&adev->uvd.ring);  in uvd_v4_2_process_interrupt()
893 	adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs;  in uvd_v4_2_set_ring_funcs()