100 	int r;  in uvd_v4_2_sw_init()  local
103 	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);  in uvd_v4_2_sw_init()
104 	if (r)  in uvd_v4_2_sw_init()
105 		return r;  in uvd_v4_2_sw_init()
107 	r = amdgpu_uvd_sw_init(adev);  in uvd_v4_2_sw_init()
108 	if (r)  in uvd_v4_2_sw_init()
109 		return r;  in uvd_v4_2_sw_init()
111 	r = amdgpu_uvd_resume(adev);  in uvd_v4_2_sw_init()
112 	if (r)  in uvd_v4_2_sw_init()
113 		return r;  in uvd_v4_2_sw_init()
117 	r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,  in uvd_v4_2_sw_init()
120 	return r;  in uvd_v4_2_sw_init()
125 	int r;  in uvd_v4_2_sw_fini()  local
128 	r = amdgpu_uvd_suspend(adev);  in uvd_v4_2_sw_fini()
129 	if (r)  in uvd_v4_2_sw_fini()
130 		return r;  in uvd_v4_2_sw_fini()
132 	r = amdgpu_uvd_sw_fini(adev);  in uvd_v4_2_sw_fini()
133 	if (r)  in uvd_v4_2_sw_fini()
134 		return r;  in uvd_v4_2_sw_fini()
136 	return r;  in uvd_v4_2_sw_fini()
151 	int r;  in uvd_v4_2_hw_init()  local
156 	r = uvd_v4_2_start(adev);  in uvd_v4_2_hw_init()
157 	if (r)  in uvd_v4_2_hw_init()
161 	r = amdgpu_ring_test_ring(ring);  in uvd_v4_2_hw_init()
162 	if (r) {  in uvd_v4_2_hw_init()
167 	r = amdgpu_ring_lock(ring, 10);  in uvd_v4_2_hw_init()
168 	if (r) {  in uvd_v4_2_hw_init()
169 		DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);  in uvd_v4_2_hw_init()
198 	if (!r)  in uvd_v4_2_hw_init()
201 	return r;  in uvd_v4_2_hw_init()
224 	int r;  in uvd_v4_2_suspend()  local
227 	r = amdgpu_uvd_suspend(adev);  in uvd_v4_2_suspend()
228 	if (r)  in uvd_v4_2_suspend()
229 		return r;  in uvd_v4_2_suspend()
231 	r = uvd_v4_2_hw_fini(adev);  in uvd_v4_2_suspend()
232 	if (r)  in uvd_v4_2_suspend()
233 		return r;  in uvd_v4_2_suspend()
235 	return r;  in uvd_v4_2_suspend()
240 	int r;  in uvd_v4_2_resume()  local
243 	r = amdgpu_uvd_resume(adev);  in uvd_v4_2_resume()
244 	if (r)  in uvd_v4_2_resume()
245 		return r;  in uvd_v4_2_resume()
247 	r = uvd_v4_2_hw_init(adev);  in uvd_v4_2_resume()
248 	if (r)  in uvd_v4_2_resume()
249 		return r;  in uvd_v4_2_resume()
251 	return r;  in uvd_v4_2_resume()
265 	int i, j, r;  in uvd_v4_2_start()  local
336 		r = 0;  in uvd_v4_2_start()
346 		r = -1;  in uvd_v4_2_start()
349 	if (r) {  in uvd_v4_2_start()
351 		return r;  in uvd_v4_2_start()
480 	int r;  in uvd_v4_2_ring_test_ring()  local
483 	r = amdgpu_ring_lock(ring, 3);  in uvd_v4_2_ring_test_ring()
484 	if (r) {  in uvd_v4_2_ring_test_ring()
486 			  ring->idx, r);  in uvd_v4_2_ring_test_ring()
487 		return r;  in uvd_v4_2_ring_test_ring()
505 		r = -EINVAL;  in uvd_v4_2_ring_test_ring()
507 	return r;  in uvd_v4_2_ring_test_ring()
538 	int r;  in uvd_v4_2_ring_test_ib()  local
540 	r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);  in uvd_v4_2_ring_test_ib()
541 	if (r) {  in uvd_v4_2_ring_test_ib()
542 		DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r);  in uvd_v4_2_ring_test_ib()
543 		return r;  in uvd_v4_2_ring_test_ib()
546 	r = amdgpu_uvd_get_create_msg(ring, 1, NULL);  in uvd_v4_2_ring_test_ib()
547 	if (r) {  in uvd_v4_2_ring_test_ib()
548 		DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);  in uvd_v4_2_ring_test_ib()
552 	r = amdgpu_uvd_get_destroy_msg(ring, 1, &fence);  in uvd_v4_2_ring_test_ib()
553 	if (r) {  in uvd_v4_2_ring_test_ib()
554 		DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);  in uvd_v4_2_ring_test_ib()
558 	r = fence_wait(fence, false);  in uvd_v4_2_ring_test_ib()
559 	if (r) {  in uvd_v4_2_ring_test_ib()
560 		DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);  in uvd_v4_2_ring_test_ib()
567 	return r;  in uvd_v4_2_ring_test_ib()