37 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);
38 static void uvd_v4_2_init_cg(struct amdgpu_device *adev);
39 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
40 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
41 static int uvd_v4_2_start(struct amdgpu_device *adev);
42 static void uvd_v4_2_stop(struct amdgpu_device *adev);
53 	struct amdgpu_device *adev = ring->adev;  in uvd_v4_2_ring_get_rptr()  local
67 	struct amdgpu_device *adev = ring->adev;  in uvd_v4_2_ring_get_wptr()  local
81 	struct amdgpu_device *adev = ring->adev;  in uvd_v4_2_ring_set_wptr()  local
88 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_early_init()  local
90 	uvd_v4_2_set_ring_funcs(adev);  in uvd_v4_2_early_init()
91 	uvd_v4_2_set_irq_funcs(adev);  in uvd_v4_2_early_init()
99 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_sw_init()  local
103 	r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);  in uvd_v4_2_sw_init()
107 	r = amdgpu_uvd_sw_init(adev);  in uvd_v4_2_sw_init()
111 	r = amdgpu_uvd_resume(adev);  in uvd_v4_2_sw_init()
115 	ring = &adev->uvd.ring;  in uvd_v4_2_sw_init()
117 	r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf,  in uvd_v4_2_sw_init()
118 			     &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);  in uvd_v4_2_sw_init()
126 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_sw_fini()  local
128 	r = amdgpu_uvd_suspend(adev);  in uvd_v4_2_sw_fini()
132 	r = amdgpu_uvd_sw_fini(adev);  in uvd_v4_2_sw_fini()
148 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_hw_init()  local
149 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v4_2_hw_init()
154 	amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);  in uvd_v4_2_hw_init()
156 	r = uvd_v4_2_start(adev);  in uvd_v4_2_hw_init()
196 	amdgpu_asic_set_uvd_clocks(adev, 0, 0);  in uvd_v4_2_hw_init()
213 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_hw_fini()  local
214 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v4_2_hw_fini()
216 	uvd_v4_2_stop(adev);  in uvd_v4_2_hw_fini()
225 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_suspend()  local
227 	r = amdgpu_uvd_suspend(adev);  in uvd_v4_2_suspend()
231 	r = uvd_v4_2_hw_fini(adev);  in uvd_v4_2_suspend()
241 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_resume()  local
243 	r = amdgpu_uvd_resume(adev);  in uvd_v4_2_resume()
247 	r = uvd_v4_2_hw_init(adev);  in uvd_v4_2_resume()
261 static int uvd_v4_2_start(struct amdgpu_device *adev)  in uvd_v4_2_start()  argument
263 	struct amdgpu_ring *ring = &adev->uvd.ring;  in uvd_v4_2_start()
271 	uvd_v4_2_mc_resume(adev);  in uvd_v4_2_start()
391 static void uvd_v4_2_stop(struct amdgpu_device *adev)  in uvd_v4_2_stop()  argument
477 	struct amdgpu_device *adev = ring->adev;  in uvd_v4_2_ring_test_ring()  local
492 	for (i = 0; i < adev->usec_timeout; i++) {  in uvd_v4_2_ring_test_ring()
499 	if (i < adev->usec_timeout) {  in uvd_v4_2_ring_test_ring()
536 	struct amdgpu_device *adev = ring->adev;  in uvd_v4_2_ring_test_ib()  local
540 	r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);  in uvd_v4_2_ring_test_ib()
566 	amdgpu_asic_set_uvd_clocks(adev, 0, 0);  in uvd_v4_2_ring_test_ib()
577 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)  in uvd_v4_2_mc_resume()  argument
583 	addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;  in uvd_v4_2_mc_resume()
584 	size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;  in uvd_v4_2_mc_resume()
599 	addr = (adev->uvd.gpu_addr >> 28) & 0xF;  in uvd_v4_2_mc_resume()
603 	addr = (adev->uvd.gpu_addr >> 32) & 0xFF;  in uvd_v4_2_mc_resume()
606 	uvd_v4_2_init_cg(adev);  in uvd_v4_2_mc_resume()
609 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,  in uvd_v4_2_enable_mgcg()  argument
614 	if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_UVD_MGCG)) {  in uvd_v4_2_enable_mgcg()
635 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,  in uvd_v4_2_set_dcm()  argument
660 static void uvd_v4_2_init_cg(struct amdgpu_device *adev)  in uvd_v4_2_init_cg()  argument
665 		uvd_v4_2_set_dcm(adev, false);  in uvd_v4_2_init_cg()
675 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_is_idle()  local
683 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_wait_for_idle()  local
685 	for (i = 0; i < adev->usec_timeout; i++) {  in uvd_v4_2_wait_for_idle()
694 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_soft_reset()  local
696 	uvd_v4_2_stop(adev);  in uvd_v4_2_soft_reset()
702 	return uvd_v4_2_start(adev);  in uvd_v4_2_soft_reset()
707 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_print_status()  local
708 	dev_info(adev->dev, "UVD 4.2 registers\n");  in uvd_v4_2_print_status()
709 	dev_info(adev->dev, "  UVD_SEMA_ADDR_LOW=0x%08X\n",  in uvd_v4_2_print_status()
711 	dev_info(adev->dev, "  UVD_SEMA_ADDR_HIGH=0x%08X\n",  in uvd_v4_2_print_status()
713 	dev_info(adev->dev, "  UVD_SEMA_CMD=0x%08X\n",  in uvd_v4_2_print_status()
715 	dev_info(adev->dev, "  UVD_GPCOM_VCPU_CMD=0x%08X\n",  in uvd_v4_2_print_status()
717 	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA0=0x%08X\n",  in uvd_v4_2_print_status()
719 	dev_info(adev->dev, "  UVD_GPCOM_VCPU_DATA1=0x%08X\n",  in uvd_v4_2_print_status()
721 	dev_info(adev->dev, "  UVD_ENGINE_CNTL=0x%08X\n",  in uvd_v4_2_print_status()
723 	dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",  in uvd_v4_2_print_status()
725 	dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",  in uvd_v4_2_print_status()
727 	dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",  in uvd_v4_2_print_status()
729 	dev_info(adev->dev, "  UVD_SEMA_CNTL=0x%08X\n",  in uvd_v4_2_print_status()
731 	dev_info(adev->dev, "  UVD_LMI_EXT40_ADDR=0x%08X\n",  in uvd_v4_2_print_status()
733 	dev_info(adev->dev, "  UVD_CTX_INDEX=0x%08X\n",  in uvd_v4_2_print_status()
735 	dev_info(adev->dev, "  UVD_CTX_DATA=0x%08X\n",  in uvd_v4_2_print_status()
737 	dev_info(adev->dev, "  UVD_CGC_GATE=0x%08X\n",  in uvd_v4_2_print_status()
739 	dev_info(adev->dev, "  UVD_CGC_CTRL=0x%08X\n",  in uvd_v4_2_print_status()
741 	dev_info(adev->dev, "  UVD_LMI_CTRL2=0x%08X\n",  in uvd_v4_2_print_status()
743 	dev_info(adev->dev, "  UVD_MASTINT_EN=0x%08X\n",  in uvd_v4_2_print_status()
745 	dev_info(adev->dev, "  UVD_LMI_ADDR_EXT=0x%08X\n",  in uvd_v4_2_print_status()
747 	dev_info(adev->dev, "  UVD_LMI_CTRL=0x%08X\n",  in uvd_v4_2_print_status()
749 	dev_info(adev->dev, "  UVD_LMI_SWAP_CNTL=0x%08X\n",  in uvd_v4_2_print_status()
751 	dev_info(adev->dev, "  UVD_MP_SWAP_CNTL=0x%08X\n",  in uvd_v4_2_print_status()
753 	dev_info(adev->dev, "  UVD_MPC_SET_MUXA0=0x%08X\n",  in uvd_v4_2_print_status()
755 	dev_info(adev->dev, "  UVD_MPC_SET_MUXA1=0x%08X\n",  in uvd_v4_2_print_status()
757 	dev_info(adev->dev, "  UVD_MPC_SET_MUXB0=0x%08X\n",  in uvd_v4_2_print_status()
759 	dev_info(adev->dev, "  UVD_MPC_SET_MUXB1=0x%08X\n",  in uvd_v4_2_print_status()
761 	dev_info(adev->dev, "  UVD_MPC_SET_MUX=0x%08X\n",  in uvd_v4_2_print_status()
763 	dev_info(adev->dev, "  UVD_MPC_SET_ALU=0x%08X\n",  in uvd_v4_2_print_status()
765 	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET0=0x%08X\n",  in uvd_v4_2_print_status()
767 	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE0=0x%08X\n",  in uvd_v4_2_print_status()
769 	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET1=0x%08X\n",  in uvd_v4_2_print_status()
771 	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE1=0x%08X\n",  in uvd_v4_2_print_status()
773 	dev_info(adev->dev, "  UVD_VCPU_CACHE_OFFSET2=0x%08X\n",  in uvd_v4_2_print_status()
775 	dev_info(adev->dev, "  UVD_VCPU_CACHE_SIZE2=0x%08X\n",  in uvd_v4_2_print_status()
777 	dev_info(adev->dev, "  UVD_VCPU_CNTL=0x%08X\n",  in uvd_v4_2_print_status()
779 	dev_info(adev->dev, "  UVD_SOFT_RESET=0x%08X\n",  in uvd_v4_2_print_status()
781 	dev_info(adev->dev, "  UVD_RBC_IB_BASE=0x%08X\n",  in uvd_v4_2_print_status()
783 	dev_info(adev->dev, "  UVD_RBC_IB_SIZE=0x%08X\n",  in uvd_v4_2_print_status()
785 	dev_info(adev->dev, "  UVD_RBC_RB_BASE=0x%08X\n",  in uvd_v4_2_print_status()
787 	dev_info(adev->dev, "  UVD_RBC_RB_RPTR=0x%08X\n",  in uvd_v4_2_print_status()
789 	dev_info(adev->dev, "  UVD_RBC_RB_WPTR=0x%08X\n",  in uvd_v4_2_print_status()
791 	dev_info(adev->dev, "  UVD_RBC_RB_WPTR_CNTL=0x%08X\n",  in uvd_v4_2_print_status()
793 	dev_info(adev->dev, "  UVD_RBC_RB_CNTL=0x%08X\n",  in uvd_v4_2_print_status()
795 	dev_info(adev->dev, "  UVD_STATUS=0x%08X\n",  in uvd_v4_2_print_status()
797 	dev_info(adev->dev, "  UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",  in uvd_v4_2_print_status()
799 	dev_info(adev->dev, "  UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",  in uvd_v4_2_print_status()
801 	dev_info(adev->dev, "  UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",  in uvd_v4_2_print_status()
803 	dev_info(adev->dev, "  UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",  in uvd_v4_2_print_status()
805 	dev_info(adev->dev, "  UVD_CONTEXT_ID=0x%08X\n",  in uvd_v4_2_print_status()
809 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,  in uvd_v4_2_set_interrupt_state()  argument
818 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,  in uvd_v4_2_process_interrupt()  argument
823 	amdgpu_fence_process(&adev->uvd.ring);  in uvd_v4_2_process_interrupt()
831 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_set_clockgating_state()  local
836 	uvd_v4_2_enable_mgcg(adev, gate);  in uvd_v4_2_set_clockgating_state()
851 	 struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in uvd_v4_2_set_powergating_state()  local
854 		uvd_v4_2_stop(adev);  in uvd_v4_2_set_powergating_state()
857 		return uvd_v4_2_start(adev);  in uvd_v4_2_set_powergating_state()
891 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev)  in uvd_v4_2_set_ring_funcs()  argument
893 	adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs;  in uvd_v4_2_set_ring_funcs()
901 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)  in uvd_v4_2_set_irq_funcs()  argument
903 	adev->uvd.irq.num_types = 1;  in uvd_v4_2_set_irq_funcs()
904 	adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;  in uvd_v4_2_set_irq_funcs()