83 	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);  in uvd_v4_2_ring_set_wptr()
274 	WREG32(mmUVD_CGC_GATE, 0);  in uvd_v4_2_start()
284 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |  in uvd_v4_2_start()
296 	WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |  in uvd_v4_2_start()
304 	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);  in uvd_v4_2_start()
305 	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);  in uvd_v4_2_start()
307 	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);  in uvd_v4_2_start()
308 	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);  in uvd_v4_2_start()
309 	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);  in uvd_v4_2_start()
310 	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);  in uvd_v4_2_start()
311 	WREG32(mmUVD_MPC_SET_ALU, 0);  in uvd_v4_2_start()
312 	WREG32(mmUVD_MPC_SET_MUX, 0x88);  in uvd_v4_2_start()
315 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);  in uvd_v4_2_start()
319 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);  in uvd_v4_2_start()
325 	WREG32(mmUVD_SOFT_RESET, 0);  in uvd_v4_2_start()
358 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);  in uvd_v4_2_start()
361 	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);  in uvd_v4_2_start()
364 	WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |  in uvd_v4_2_start()
368 	WREG32(mmUVD_RBC_RB_RPTR, 0x0);  in uvd_v4_2_start()
371 	WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);  in uvd_v4_2_start()
374 	WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);  in uvd_v4_2_start()
394 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);  in uvd_v4_2_stop()
401 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);  in uvd_v4_2_stop()
405 	WREG32(mmUVD_VCPU_CNTL, 0x0);  in uvd_v4_2_stop()
482 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);  in uvd_v4_2_ring_test_ring()
585 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);  in uvd_v4_2_mc_resume()
586 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);  in uvd_v4_2_mc_resume()
590 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);  in uvd_v4_2_mc_resume()
591 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);  in uvd_v4_2_mc_resume()
595 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);  in uvd_v4_2_mc_resume()
596 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);  in uvd_v4_2_mc_resume()
600 	WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));  in uvd_v4_2_mc_resume()
604 	WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));  in uvd_v4_2_mc_resume()
622 			WREG32(mmUVD_CGC_CTRL, data);  in uvd_v4_2_enable_mgcg()
631 			WREG32(mmUVD_CGC_CTRL, data);  in uvd_v4_2_enable_mgcg()
656 	WREG32(mmUVD_CGC_CTRL, tmp);  in uvd_v4_2_set_dcm()
669 		WREG32(mmUVD_CGC_CTRL, tmp);  in uvd_v4_2_init_cg()