173 	tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);  in uvd_v4_2_hw_init()
177 	tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v4_2_hw_init()
181 	tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);  in uvd_v4_2_hw_init()
186 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));  in uvd_v4_2_hw_init()
189 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));  in uvd_v4_2_hw_init()
424 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v4_2_ring_emit_fence()
426 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v4_2_ring_emit_fence()
428 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v4_2_ring_emit_fence()
430 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v4_2_ring_emit_fence()
433 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));  in uvd_v4_2_ring_emit_fence()
435 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));  in uvd_v4_2_ring_emit_fence()
437 	amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));  in uvd_v4_2_ring_emit_fence()
456 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0));  in uvd_v4_2_ring_emit_semaphore()
459 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0));  in uvd_v4_2_ring_emit_semaphore()
462 	amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0));  in uvd_v4_2_ring_emit_semaphore()
489 	amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));  in uvd_v4_2_ring_test_ring()
521 	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));  in uvd_v4_2_ring_emit_ib()
523 	amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));  in uvd_v4_2_ring_emit_ib()