49 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev);
58 static void tonga_ih_enable_interrupts(struct amdgpu_device *adev)  in tonga_ih_enable_interrupts()  argument
65 	adev->irq.ih.enabled = true;  in tonga_ih_enable_interrupts()
75 static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)  in tonga_ih_disable_interrupts()  argument
85 	adev->irq.ih.enabled = false;  in tonga_ih_disable_interrupts()
86 	adev->irq.ih.rptr = 0;  in tonga_ih_disable_interrupts()
100 static int tonga_ih_irq_init(struct amdgpu_device *adev)  in tonga_ih_irq_init()  argument
108 	tonga_ih_disable_interrupts(adev);  in tonga_ih_irq_init()
111 	WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8);  in tonga_ih_irq_init()
122 	if (adev->irq.ih.use_bus_addr)  in tonga_ih_irq_init()
123 		WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);  in tonga_ih_irq_init()
125 		WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);  in tonga_ih_irq_init()
127 	rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);  in tonga_ih_irq_init()
134 	if (adev->irq.msi_enabled)  in tonga_ih_irq_init()
140 	if (adev->irq.ih.use_bus_addr)  in tonga_ih_irq_init()
141 		wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4);  in tonga_ih_irq_init()
143 		wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);  in tonga_ih_irq_init()
152 	if (adev->irq.ih.use_doorbell) {  in tonga_ih_irq_init()
154 						 OFFSET, adev->irq.ih.doorbell_index);  in tonga_ih_irq_init()
163 	pci_set_master(adev->pdev);  in tonga_ih_irq_init()
166 	tonga_ih_enable_interrupts(adev);  in tonga_ih_irq_init()
178 static void tonga_ih_irq_disable(struct amdgpu_device *adev)  in tonga_ih_irq_disable()  argument
180 	tonga_ih_disable_interrupts(adev);  in tonga_ih_irq_disable()
197 static u32 tonga_ih_get_wptr(struct amdgpu_device *adev)  in tonga_ih_get_wptr()  argument
201 	if (adev->irq.ih.use_bus_addr)  in tonga_ih_get_wptr()
202 		wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]);  in tonga_ih_get_wptr()
204 		wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);  in tonga_ih_get_wptr()
212 		dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",  in tonga_ih_get_wptr()
213 			wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);  in tonga_ih_get_wptr()
214 		adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;  in tonga_ih_get_wptr()
219 	return (wptr & adev->irq.ih.ptr_mask);  in tonga_ih_get_wptr()
230 static void tonga_ih_decode_iv(struct amdgpu_device *adev,  in tonga_ih_decode_iv()  argument
234 	u32 ring_index = adev->irq.ih.rptr >> 2;  in tonga_ih_decode_iv()
237 	dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);  in tonga_ih_decode_iv()
238 	dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);  in tonga_ih_decode_iv()
239 	dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);  in tonga_ih_decode_iv()
240 	dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);  in tonga_ih_decode_iv()
249 	adev->irq.ih.rptr += 16;  in tonga_ih_decode_iv()
259 static void tonga_ih_set_rptr(struct amdgpu_device *adev)  in tonga_ih_set_rptr()  argument
261 	if (adev->irq.ih.use_doorbell) {  in tonga_ih_set_rptr()
263 		if (adev->irq.ih.use_bus_addr)  in tonga_ih_set_rptr()
264 			adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;  in tonga_ih_set_rptr()
266 			adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr;  in tonga_ih_set_rptr()
267 		WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr);  in tonga_ih_set_rptr()
269 		WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);  in tonga_ih_set_rptr()
275 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in tonga_ih_early_init()  local
277 	tonga_ih_set_interrupt_funcs(adev);  in tonga_ih_early_init()
284 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in tonga_ih_sw_init()  local
286 	r = amdgpu_ih_ring_init(adev, 4 * 1024, true);  in tonga_ih_sw_init()
290 	adev->irq.ih.use_doorbell = true;  in tonga_ih_sw_init()
291 	adev->irq.ih.doorbell_index = AMDGPU_DOORBELL_IH;  in tonga_ih_sw_init()
293 	r = amdgpu_irq_init(adev);  in tonga_ih_sw_init()
300 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in tonga_ih_sw_fini()  local
302 	amdgpu_irq_fini(adev);  in tonga_ih_sw_fini()
303 	amdgpu_ih_ring_fini(adev);  in tonga_ih_sw_fini()
311 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in tonga_ih_hw_init()  local
313 	r = tonga_ih_irq_init(adev);  in tonga_ih_hw_init()
322 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in tonga_ih_hw_fini()  local
324 	tonga_ih_irq_disable(adev);  in tonga_ih_hw_fini()
331 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in tonga_ih_suspend()  local
333 	return tonga_ih_hw_fini(adev);  in tonga_ih_suspend()
338 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in tonga_ih_resume()  local
340 	return tonga_ih_hw_init(adev);  in tonga_ih_resume()
345 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in tonga_ih_is_idle()  local
358 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in tonga_ih_wait_for_idle()  local
360 	for (i = 0; i < adev->usec_timeout; i++) {  in tonga_ih_wait_for_idle()
372 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in tonga_ih_print_status()  local
374 	dev_info(adev->dev, "TONGA IH registers\n");  in tonga_ih_print_status()
375 	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",  in tonga_ih_print_status()
377 	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",  in tonga_ih_print_status()
379 	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",  in tonga_ih_print_status()
381 	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",  in tonga_ih_print_status()
383 	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",  in tonga_ih_print_status()
385 	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",  in tonga_ih_print_status()
387 	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",  in tonga_ih_print_status()
389 	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",  in tonga_ih_print_status()
391 	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",  in tonga_ih_print_status()
393 	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",  in tonga_ih_print_status()
395 	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",  in tonga_ih_print_status()
402 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;  in tonga_ih_soft_reset()  local
410 		tonga_ih_print_status(adev);  in tonga_ih_soft_reset()
414 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in tonga_ih_soft_reset()
427 		tonga_ih_print_status(adev);  in tonga_ih_soft_reset()
468 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev)  in tonga_ih_set_interrupt_funcs()  argument
470 	if (adev->irq.ih_funcs == NULL)  in tonga_ih_set_interrupt_funcs()
471 		adev->irq.ih_funcs = &tonga_ih_funcs;  in tonga_ih_set_interrupt_funcs()