232 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v3_0_init_microcode()
237 		err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);  in sdma_v3_0_init_microcode()
240 		err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);  in sdma_v3_0_init_microcode()
243 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;  in sdma_v3_0_init_microcode()
244 		adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);  in sdma_v3_0_init_microcode()
245 		adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);  in sdma_v3_0_init_microcode()
246 		if (adev->sdma.instance[i].feature_version >= 20)  in sdma_v3_0_init_microcode()
247 			adev->sdma.instance[i].burst_nop = true;  in sdma_v3_0_init_microcode()
252 			info->fw = adev->sdma.instance[i].fw;  in sdma_v3_0_init_microcode()
263 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v3_0_init_microcode()
264 			release_firmware(adev->sdma.instance[i].fw);  in sdma_v3_0_init_microcode()
265 			adev->sdma.instance[i].fw = NULL;  in sdma_v3_0_init_microcode()
304 		int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;  in sdma_v3_0_ring_get_wptr()
328 		int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;  in sdma_v3_0_ring_set_wptr()
336 	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);  in sdma_v3_0_ring_insert_nop()  local
340 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v3_0_ring_insert_nop()
397 	if (ring == &ring->adev->sdma.instance[0].ring)  in sdma_v3_0_ring_emit_hdp_flush()
482 	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;  in sdma_v3_0_gfx_stop()
483 	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;  in sdma_v3_0_gfx_stop()
491 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v3_0_gfx_stop()
528 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v3_0_ctx_switch_enable()
558 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v3_0_enable()
585 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v3_0_gfx_resume()
586 		ring = &adev->sdma.instance[i].ring;  in sdma_v3_0_gfx_resume()
700 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v3_0_load_microcode()
701 		if (!adev->sdma.instance[i].fw)  in sdma_v3_0_load_microcode()
703 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;  in sdma_v3_0_load_microcode()
707 			(adev->sdma.instance[i].fw->data +  in sdma_v3_0_load_microcode()
712 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);  in sdma_v3_0_load_microcode()
735 		for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v3_0_start()
1040 	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);  in sdma_v3_0_vm_pad_ib()  local
1046 		if (sdma && sdma->burst_nop && (i == 0))  in sdma_v3_0_vm_pad_ib()
1100 		adev->sdma.num_instances = 1;  in sdma_v3_0_early_init()
1103 		adev->sdma.num_instances = SDMA_MAX_INSTANCE;  in sdma_v3_0_early_init()
1122 	r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);  in sdma_v3_0_sw_init()
1127 	r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);  in sdma_v3_0_sw_init()
1132 	r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);  in sdma_v3_0_sw_init()
1142 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v3_0_sw_init()
1143 		ring = &adev->sdma.instance[i].ring;  in sdma_v3_0_sw_init()
1152 				     &adev->sdma.trap_irq,  in sdma_v3_0_sw_init()
1168 	for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v3_0_sw_fini()
1169 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in sdma_v3_0_sw_fini()
1249 	for (i = 0; i < adev->sdma.num_instances; i++) {  in sdma_v3_0_print_status()
1394 			amdgpu_fence_process(&adev->sdma.instance[0].ring);  in sdma_v3_0_process_trap_irq()
1407 			amdgpu_fence_process(&adev->sdma.instance[1].ring);  in sdma_v3_0_process_trap_irq()
1478 	for (i = 0; i < adev->sdma.num_instances; i++)  in sdma_v3_0_set_ring_funcs()
1479 		adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;  in sdma_v3_0_set_ring_funcs()
1493 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;  in sdma_v3_0_set_irq_funcs()
1494 	adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;  in sdma_v3_0_set_irq_funcs()
1495 	adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;  in sdma_v3_0_set_irq_funcs()
1561 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v3_0_set_buffer_funcs()
1576 		adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v3_0_set_vm_pte_funcs()