330 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);  in sdma_v3_0_ring_set_wptr()
494 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in sdma_v3_0_gfx_stop()
497 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);  in sdma_v3_0_gfx_stop()
536 		WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);  in sdma_v3_0_ctx_switch_enable()
564 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);  in sdma_v3_0_enable()
593 			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);  in sdma_v3_0_gfx_resume()
594 			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);  in sdma_v3_0_gfx_resume()
599 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);  in sdma_v3_0_gfx_resume()
610 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in sdma_v3_0_gfx_resume()
613 		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);  in sdma_v3_0_gfx_resume()
614 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);  in sdma_v3_0_gfx_resume()
617 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],  in sdma_v3_0_gfx_resume()
619 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],  in sdma_v3_0_gfx_resume()
624 		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);  in sdma_v3_0_gfx_resume()
625 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);  in sdma_v3_0_gfx_resume()
628 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);  in sdma_v3_0_gfx_resume()
639 		WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);  in sdma_v3_0_gfx_resume()
643 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in sdma_v3_0_gfx_resume()
651 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);  in sdma_v3_0_gfx_resume()
709 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);  in sdma_v3_0_load_microcode()
711 			WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));  in sdma_v3_0_load_microcode()
712 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);  in sdma_v3_0_load_microcode()
1300 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in sdma_v3_0_soft_reset()
1307 		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in sdma_v3_0_soft_reset()
1317 		WREG32(mmSRBM_SOFT_RESET, tmp);  in sdma_v3_0_soft_reset()
1323 		WREG32(mmSRBM_SOFT_RESET, tmp);  in sdma_v3_0_soft_reset()
1348 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);  in sdma_v3_0_set_trap_irq_state()
1353 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);  in sdma_v3_0_set_trap_irq_state()
1364 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);  in sdma_v3_0_set_trap_irq_state()
1369 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);  in sdma_v3_0_set_trap_irq_state()