182 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)  in sdma_v2_4_ring_get_rptr()  argument
187 	rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;  in sdma_v2_4_ring_get_rptr()
199 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)  in sdma_v2_4_ring_get_wptr()  argument
201 	struct amdgpu_device *adev = ring->adev;  in sdma_v2_4_ring_get_wptr()
202 	int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;  in sdma_v2_4_ring_get_wptr()
215 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)  in sdma_v2_4_ring_set_wptr()  argument
217 	struct amdgpu_device *adev = ring->adev;  in sdma_v2_4_ring_set_wptr()
218 	int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;  in sdma_v2_4_ring_set_wptr()
220 	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);  in sdma_v2_4_ring_set_wptr()
223 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)  in sdma_v2_4_ring_insert_nop()  argument
225 	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);  in sdma_v2_4_ring_insert_nop()
230 			amdgpu_ring_write(ring, ring->nop |  in sdma_v2_4_ring_insert_nop()
233 			amdgpu_ring_write(ring, ring->nop);  in sdma_v2_4_ring_insert_nop()
244 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,  in sdma_v2_4_ring_emit_ib()  argument
247 	u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf;  in sdma_v2_4_ring_emit_ib()
248 	u32 next_rptr = ring->wptr + 5;  in sdma_v2_4_ring_emit_ib()
255 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |  in sdma_v2_4_ring_emit_ib()
257 	amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);  in sdma_v2_4_ring_emit_ib()
258 	amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));  in sdma_v2_4_ring_emit_ib()
259 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));  in sdma_v2_4_ring_emit_ib()
260 	amdgpu_ring_write(ring, next_rptr);  in sdma_v2_4_ring_emit_ib()
263 	sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);  in sdma_v2_4_ring_emit_ib()
265 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |  in sdma_v2_4_ring_emit_ib()
268 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);  in sdma_v2_4_ring_emit_ib()
269 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in sdma_v2_4_ring_emit_ib()
270 	amdgpu_ring_write(ring, ib->length_dw);  in sdma_v2_4_ring_emit_ib()
271 	amdgpu_ring_write(ring, 0);  in sdma_v2_4_ring_emit_ib()
272 	amdgpu_ring_write(ring, 0);  in sdma_v2_4_ring_emit_ib()
283 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)  in sdma_v2_4_ring_emit_hdp_flush()  argument
287 	if (ring == &ring->adev->sdma.instance[0].ring)  in sdma_v2_4_ring_emit_hdp_flush()
292 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |  in sdma_v2_4_ring_emit_hdp_flush()
295 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);  in sdma_v2_4_ring_emit_hdp_flush()
296 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);  in sdma_v2_4_ring_emit_hdp_flush()
297 	amdgpu_ring_write(ring, ref_and_mask); /* reference */  in sdma_v2_4_ring_emit_hdp_flush()
298 	amdgpu_ring_write(ring, ref_and_mask); /* mask */  in sdma_v2_4_ring_emit_hdp_flush()
299 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |  in sdma_v2_4_ring_emit_hdp_flush()
313 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,  in sdma_v2_4_ring_emit_fence()  argument
318 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));  in sdma_v2_4_ring_emit_fence()
319 	amdgpu_ring_write(ring, lower_32_bits(addr));  in sdma_v2_4_ring_emit_fence()
320 	amdgpu_ring_write(ring, upper_32_bits(addr));  in sdma_v2_4_ring_emit_fence()
321 	amdgpu_ring_write(ring, lower_32_bits(seq));  in sdma_v2_4_ring_emit_fence()
326 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));  in sdma_v2_4_ring_emit_fence()
327 		amdgpu_ring_write(ring, lower_32_bits(addr));  in sdma_v2_4_ring_emit_fence()
328 		amdgpu_ring_write(ring, upper_32_bits(addr));  in sdma_v2_4_ring_emit_fence()
329 		amdgpu_ring_write(ring, upper_32_bits(seq));  in sdma_v2_4_ring_emit_fence()
333 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));  in sdma_v2_4_ring_emit_fence()
334 	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));  in sdma_v2_4_ring_emit_fence()
347 static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,  in sdma_v2_4_ring_emit_semaphore()  argument
354 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) |  in sdma_v2_4_ring_emit_semaphore()
356 	amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8);  in sdma_v2_4_ring_emit_semaphore()
357 	amdgpu_ring_write(ring, upper_32_bits(addr));  in sdma_v2_4_ring_emit_semaphore()
371 	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;  in sdma_v2_4_gfx_stop()
372 	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;  in sdma_v2_4_gfx_stop()
442 	struct amdgpu_ring *ring;  in sdma_v2_4_gfx_resume()  local
449 		ring = &adev->sdma.instance[i].ring;  in sdma_v2_4_gfx_resume()
450 		wb_offset = (ring->rptr_offs * 4);  in sdma_v2_4_gfx_resume()
465 		rb_bufsz = order_base_2(ring->ring_size / 4);  in sdma_v2_4_gfx_resume()
487 		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);  in sdma_v2_4_gfx_resume()
488 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);  in sdma_v2_4_gfx_resume()
490 		ring->wptr = 0;  in sdma_v2_4_gfx_resume()
491 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);  in sdma_v2_4_gfx_resume()
505 		ring->ready = true;  in sdma_v2_4_gfx_resume()
507 		r = amdgpu_ring_test_ring(ring);  in sdma_v2_4_gfx_resume()
509 			ring->ready = false;  in sdma_v2_4_gfx_resume()
513 		if (adev->mman.buffer_funcs_ring == ring)  in sdma_v2_4_gfx_resume()
620 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)  in sdma_v2_4_ring_test_ring()  argument
622 	struct amdgpu_device *adev = ring->adev;  in sdma_v2_4_ring_test_ring()
639 	r = amdgpu_ring_lock(ring, 5);  in sdma_v2_4_ring_test_ring()
641 		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);  in sdma_v2_4_ring_test_ring()
646 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |  in sdma_v2_4_ring_test_ring()
648 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));  in sdma_v2_4_ring_test_ring()
649 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));  in sdma_v2_4_ring_test_ring()
650 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));  in sdma_v2_4_ring_test_ring()
651 	amdgpu_ring_write(ring, 0xDEADBEEF);  in sdma_v2_4_ring_test_ring()
652 	amdgpu_ring_unlock_commit(ring);  in sdma_v2_4_ring_test_ring()
662 		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);  in sdma_v2_4_ring_test_ring()
665 			  ring->idx, tmp);  in sdma_v2_4_ring_test_ring()
681 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)  in sdma_v2_4_ring_test_ib()  argument
683 	struct amdgpu_device *adev = ring->adev;  in sdma_v2_4_ring_test_ib()
702 	r = amdgpu_ib_get(ring, NULL, 256, &ib);  in sdma_v2_4_ring_test_ib()
719 	r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,  in sdma_v2_4_ring_test_ib()
738 			 ring->idx, i);  in sdma_v2_4_ring_test_ib()
820 				value = amdgpu_vm_map_gart(ib->ring->adev, addr);  in sdma_v2_4_vm_write_pte()
891 	struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);  in sdma_v2_4_vm_pad_ib()
915 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,  in sdma_v2_4_ring_emit_vm_flush()  argument
918 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |  in sdma_v2_4_ring_emit_vm_flush()
921 		amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));  in sdma_v2_4_ring_emit_vm_flush()
923 		amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));  in sdma_v2_4_ring_emit_vm_flush()
925 	amdgpu_ring_write(ring, pd_addr >> 12);  in sdma_v2_4_ring_emit_vm_flush()
928 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |  in sdma_v2_4_ring_emit_vm_flush()
930 	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);  in sdma_v2_4_ring_emit_vm_flush()
931 	amdgpu_ring_write(ring, 1 << vm_id);  in sdma_v2_4_ring_emit_vm_flush()
934 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |  in sdma_v2_4_ring_emit_vm_flush()
937 	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);  in sdma_v2_4_ring_emit_vm_flush()
938 	amdgpu_ring_write(ring, 0);  in sdma_v2_4_ring_emit_vm_flush()
939 	amdgpu_ring_write(ring, 0); /* reference */  in sdma_v2_4_ring_emit_vm_flush()
940 	amdgpu_ring_write(ring, 0); /* mask */  in sdma_v2_4_ring_emit_vm_flush()
941 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |  in sdma_v2_4_ring_emit_vm_flush()
961 	struct amdgpu_ring *ring;  in sdma_v2_4_sw_init()  local
987 		ring = &adev->sdma.instance[i].ring;  in sdma_v2_4_sw_init()
988 		ring->ring_obj = NULL;  in sdma_v2_4_sw_init()
989 		ring->use_doorbell = false;  in sdma_v2_4_sw_init()
990 		sprintf(ring->name, "sdma%d", i);  in sdma_v2_4_sw_init()
991 		r = amdgpu_ring_init(adev, ring, 256 * 1024,  in sdma_v2_4_sw_init()
1010 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);  in sdma_v2_4_sw_fini()
1232 			amdgpu_fence_process(&adev->sdma.instance[0].ring);  in sdma_v2_4_process_trap_irq()
1245 			amdgpu_fence_process(&adev->sdma.instance[1].ring);  in sdma_v2_4_process_trap_irq()
1318 		adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;  in sdma_v2_4_set_ring_funcs()
1400 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v2_4_set_buffer_funcs()
1415 		adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;  in sdma_v2_4_set_vm_pte_funcs()