220 	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);  in sdma_v2_4_ring_set_wptr()
383 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in sdma_v2_4_gfx_stop()
386 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);  in sdma_v2_4_gfx_stop()
428 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);  in sdma_v2_4_enable()
456 			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);  in sdma_v2_4_gfx_resume()
457 			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);  in sdma_v2_4_gfx_resume()
462 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);  in sdma_v2_4_gfx_resume()
473 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in sdma_v2_4_gfx_resume()
476 		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);  in sdma_v2_4_gfx_resume()
477 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);  in sdma_v2_4_gfx_resume()
480 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],  in sdma_v2_4_gfx_resume()
482 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],  in sdma_v2_4_gfx_resume()
487 		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);  in sdma_v2_4_gfx_resume()
488 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);  in sdma_v2_4_gfx_resume()
491 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);  in sdma_v2_4_gfx_resume()
495 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in sdma_v2_4_gfx_resume()
503 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);  in sdma_v2_4_gfx_resume()
561 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);  in sdma_v2_4_load_microcode()
563 			WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));  in sdma_v2_4_load_microcode()
564 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);  in sdma_v2_4_load_microcode()
1138 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in sdma_v2_4_soft_reset()
1145 		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in sdma_v2_4_soft_reset()
1155 		WREG32(mmSRBM_SOFT_RESET, tmp);  in sdma_v2_4_soft_reset()
1161 		WREG32(mmSRBM_SOFT_RESET, tmp);  in sdma_v2_4_soft_reset()
1186 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);  in sdma_v2_4_set_trap_irq_state()
1191 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);  in sdma_v2_4_set_trap_irq_state()
1202 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);  in sdma_v2_4_set_trap_irq_state()
1207 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);  in sdma_v2_4_set_trap_irq_state()