145 						      ATOM_AVAILABLE_SCLK_LIST *table)  in sumo_construct_sclk_voltage_mapping_table()  argument
152 		if (table[i].ulSupportedSCLK > prev_sclk) {  in sumo_construct_sclk_voltage_mapping_table()
154 				table[i].ulSupportedSCLK;  in sumo_construct_sclk_voltage_mapping_table()
156 				table[i].usVoltageIndex;  in sumo_construct_sclk_voltage_mapping_table()
157 			prev_sclk = table[i].ulSupportedSCLK;  in sumo_construct_sclk_voltage_mapping_table()
167 					     ATOM_AVAILABLE_SCLK_LIST *table)  in sumo_construct_vid_mapping_table()  argument
172 		if (table[i].ulSupportedSCLK != 0) {  in sumo_construct_vid_mapping_table()
173 			vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =  in sumo_construct_vid_mapping_table()
174 				table[i].usVoltageID;  in sumo_construct_vid_mapping_table()
175 			vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =  in sumo_construct_vid_mapping_table()
176 				table[i].usVoltageIndex;  in sumo_construct_vid_mapping_table()
807 	struct amdgpu_clock_voltage_dependency_table *table =  in kv_program_bootup_state()  local
810 	if (table && table->count) {  in kv_program_bootup_state()
812 			if (table->entries[i].clk == pi->boot_pl.sclk)  in kv_program_bootup_state()
819 		struct sumo_sclk_voltage_mapping_table *table =  in kv_program_bootup_state()  local
822 		if (table->num_max_dpm_entries == 0)  in kv_program_bootup_state()
826 			if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)  in kv_program_bootup_state()
909 	struct amdgpu_uvd_clock_voltage_dependency_table *table =  in kv_populate_uvd_table()  local
915 	if (table == NULL || table->count == 0)  in kv_populate_uvd_table()
919 	for (i = 0; i < table->count; i++) {  in kv_populate_uvd_table()
921 		    (pi->high_voltage_t < table->entries[i].v))  in kv_populate_uvd_table()
924 		pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);  in kv_populate_uvd_table()
925 		pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);  in kv_populate_uvd_table()
926 		pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);  in kv_populate_uvd_table()
929 			(u8)kv_get_clk_bypass(adev, table->entries[i].vclk);  in kv_populate_uvd_table()
931 			(u8)kv_get_clk_bypass(adev, table->entries[i].dclk);  in kv_populate_uvd_table()
934 							 table->entries[i].vclk, false, &dividers);  in kv_populate_uvd_table()
940 							 table->entries[i].dclk, false, &dividers);  in kv_populate_uvd_table()
982 	struct amdgpu_vce_clock_voltage_dependency_table *table =  in kv_populate_vce_table()  local
986 	if (table == NULL || table->count == 0)  in kv_populate_vce_table()
990 	for (i = 0; i < table->count; i++) {  in kv_populate_vce_table()
992 		    pi->high_voltage_t < table->entries[i].v)  in kv_populate_vce_table()
995 		pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);  in kv_populate_vce_table()
996 		pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);  in kv_populate_vce_table()
999 			(u8)kv_get_clk_bypass(adev, table->entries[i].evclk);  in kv_populate_vce_table()
1002 							 table->entries[i].evclk, false, &dividers);  in kv_populate_vce_table()
1043 	struct amdgpu_clock_voltage_dependency_table *table =  in kv_populate_samu_table()  local
1049 	if (table == NULL || table->count == 0)  in kv_populate_samu_table()
1053 	for (i = 0; i < table->count; i++) {  in kv_populate_samu_table()
1055 		    pi->high_voltage_t < table->entries[i].v)  in kv_populate_samu_table()
1058 		pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);  in kv_populate_samu_table()
1059 		pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);  in kv_populate_samu_table()
1062 			(u8)kv_get_clk_bypass(adev, table->entries[i].clk);  in kv_populate_samu_table()
1065 							 table->entries[i].clk, false, &dividers);  in kv_populate_samu_table()
1109 	struct amdgpu_clock_voltage_dependency_table *table =  in kv_populate_acp_table()  local
1115 	if (table == NULL || table->count == 0)  in kv_populate_acp_table()
1119 	for (i = 0; i < table->count; i++) {  in kv_populate_acp_table()
1120 		pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);  in kv_populate_acp_table()
1121 		pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);  in kv_populate_acp_table()
1124 							 table->entries[i].clk, false, &dividers);  in kv_populate_acp_table()
1168 	struct amdgpu_clock_voltage_dependency_table *table =  in kv_calculate_dfs_bypass_settings()  local
1171 	if (table && table->count) {  in kv_calculate_dfs_bypass_settings()
1174 				if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)  in kv_calculate_dfs_bypass_settings()
1176 				else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)  in kv_calculate_dfs_bypass_settings()
1178 				else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)  in kv_calculate_dfs_bypass_settings()
1180 				else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)  in kv_calculate_dfs_bypass_settings()
1182 				else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)  in kv_calculate_dfs_bypass_settings()
1191 		struct sumo_sclk_voltage_mapping_table *table =  in kv_calculate_dfs_bypass_settings()  local
1195 				if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)  in kv_calculate_dfs_bypass_settings()
1197 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)  in kv_calculate_dfs_bypass_settings()
1199 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)  in kv_calculate_dfs_bypass_settings()
1201 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)  in kv_calculate_dfs_bypass_settings()
1203 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)  in kv_calculate_dfs_bypass_settings()
1496 	struct amdgpu_uvd_clock_voltage_dependency_table *table =  in kv_update_uvd_dpm()  local
1502 		if (table->count)  in kv_update_uvd_dpm()
1503 			pi->uvd_boot_level = table->count - 1;  in kv_update_uvd_dpm()
1532 	struct amdgpu_vce_clock_voltage_dependency_table *table =  in kv_get_vce_boot_level()  local
1535 	for (i = 0; i < table->count; i++) {  in kv_get_vce_boot_level()
1536 		if (table->entries[i].evclk >= evclk)  in kv_get_vce_boot_level()
1548 	struct amdgpu_vce_clock_voltage_dependency_table *table =  in kv_update_vce_dpm()  local
1560 			pi->vce_boot_level = table->count - 1;  in kv_update_vce_dpm()
1595 	struct amdgpu_clock_voltage_dependency_table *table =  in kv_update_samu_dpm()  local
1601 			pi->samu_boot_level = table->count - 1;  in kv_update_samu_dpm()
1626 	struct amdgpu_clock_voltage_dependency_table *table =  in kv_get_acp_boot_level()  local
1629 	for (i = 0; i < table->count; i++) {  in kv_get_acp_boot_level()
1630 		if (table->entries[i].clk >= 0) /* XXX */  in kv_get_acp_boot_level()
1634 	if (i >= table->count)  in kv_get_acp_boot_level()
1635 		i = table->count - 1;  in kv_get_acp_boot_level()
1659 	struct amdgpu_clock_voltage_dependency_table *table =  in kv_update_acp_dpm()  local
1665 			pi->acp_boot_level = table->count - 1;  in kv_update_acp_dpm()
1807 	struct amdgpu_clock_voltage_dependency_table *table =  in kv_set_valid_clock_range()  local
1810 	if (table && table->count) {  in kv_set_valid_clock_range()
1812 			if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||  in kv_set_valid_clock_range()
1820 			if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)  in kv_set_valid_clock_range()
1826 			if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >  in kv_set_valid_clock_range()
1827 			    (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))  in kv_set_valid_clock_range()
1833 		struct sumo_sclk_voltage_mapping_table *table =  in kv_set_valid_clock_range()  local
1837 			if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||  in kv_set_valid_clock_range()
1845 			if (table->entries[i].sclk_frequency <=  in kv_set_valid_clock_range()
1853 			     table->entries[pi->highest_valid].sclk_frequency) >  in kv_set_valid_clock_range()
1854 			    (table->entries[pi->lowest_valid].sclk_frequency -  in kv_set_valid_clock_range()
2061 						struct amdgpu_clock_and_voltage_limits *table)  in kv_construct_max_power_limits_table()  argument
2067 		table->sclk =  in kv_construct_max_power_limits_table()
2069 		table->vddc =  in kv_construct_max_power_limits_table()
2074 	table->mclk = pi->sys_info.nbp_memory_clock[0];  in kv_construct_max_power_limits_table()
2200 	struct amdgpu_clock_voltage_dependency_table *table =  in kv_get_high_voltage_limit()  local
2204 	if (table && table->count) {  in kv_get_high_voltage_limit()
2205 		for (i = table->count - 1; i >= 0; i--) {  in kv_get_high_voltage_limit()
2207 			    (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=  in kv_get_high_voltage_limit()
2214 		struct sumo_sclk_voltage_mapping_table *table =  in kv_get_high_voltage_limit()  local
2217 		for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {  in kv_get_high_voltage_limit()
2219 			    (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <=  in kv_get_high_voltage_limit()
2241 	struct amdgpu_clock_voltage_dependency_table *table =  in kv_apply_state_adjust_rules()  local
2261 		for (i = table->count - 1; i >= 0; i++) {  in kv_apply_state_adjust_rules()
2262 			if (stable_p_state_sclk >= table->entries[i].clk) {  in kv_apply_state_adjust_rules()
2263 				stable_p_state_sclk = table->entries[i].clk;  in kv_apply_state_adjust_rules()
2269 			stable_p_state_sclk = table->entries[0].clk;  in kv_apply_state_adjust_rules()
2286 	if (table && table->count) {  in kv_apply_state_adjust_rules()
2292 				ps->levels[i].sclk = table->entries[limit].clk;  in kv_apply_state_adjust_rules()
2296 		struct sumo_sclk_voltage_mapping_table *table =  in kv_apply_state_adjust_rules()  local
2304 				ps->levels[i].sclk = table->entries[limit].sclk_frequency;  in kv_apply_state_adjust_rules()
2445 	struct amdgpu_clock_voltage_dependency_table *table =  in kv_init_graphics_levels()  local
2448 	if (table && table->count) {  in kv_init_graphics_levels()
2452 		for (i = 0; i < table->count; i++) {  in kv_init_graphics_levels()
2455 			     kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))  in kv_init_graphics_levels()
2458 			kv_set_divider_value(adev, i, table->entries[i].clk);  in kv_init_graphics_levels()
2461 							   table->entries[i].v);  in kv_init_graphics_levels()
2468 		struct sumo_sclk_voltage_mapping_table *table =  in kv_init_graphics_levels()  local
2472 		for (i = 0; i < table->num_max_dpm_entries; i++) {  in kv_init_graphics_levels()
2475 			    kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit))  in kv_init_graphics_levels()
2478 			kv_set_divider_value(adev, i, table->entries[i].sclk_frequency);  in kv_init_graphics_levels()
2479 			kv_set_vid(adev, i, table->entries[i].vid_2bit);  in kv_init_graphics_levels()