1812 			if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||  in kv_set_valid_clock_range()
1820 			if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)  in kv_set_valid_clock_range()
1826 			if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >  in kv_set_valid_clock_range()
1827 			    (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))  in kv_set_valid_clock_range()
1837 			if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||  in kv_set_valid_clock_range()
1846 			    new_ps->levels[new_ps->num_levels - 1].sclk)  in kv_set_valid_clock_range()
1852 			if ((new_ps->levels[0].sclk -  in kv_set_valid_clock_range()
1855 			     new_ps->levels[new_ps->num_levels -1].sclk))  in kv_set_valid_clock_range()
2282 		if (ps->levels[i].sclk < sclk)  in kv_apply_state_adjust_rules()
2283 			ps->levels[i].sclk = sclk;  in kv_apply_state_adjust_rules()
2290 			     kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {  in kv_apply_state_adjust_rules()
2292 				ps->levels[i].sclk = table->entries[limit].clk;  in kv_apply_state_adjust_rules()
2302 			     kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) {  in kv_apply_state_adjust_rules()
2304 				ps->levels[i].sclk = table->entries[limit].sclk_frequency;  in kv_apply_state_adjust_rules()
2311 			ps->levels[i].sclk = stable_p_state_sclk;  in kv_apply_state_adjust_rules()
2676 	ps->levels[0] = pi->boot_pl;  in kv_patch_boot_state()
2712 	struct kv_pl *pl = &ps->levels[index];  in kv_parse_pplib_clock_info()
2923 		struct kv_pl *pl = &ps->levels[i];  in kv_dpm_print_power_state()
2954 		return requested_state->levels[0].sclk;  in kv_dpm_get_sclk()
2956 		return requested_state->levels[requested_state->num_levels - 1].sclk;  in kv_dpm_get_sclk()