Lines Matching refs:dpm
78 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
100 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
384 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi()
808 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
910 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
983 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
1044 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1110 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1169 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1356 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); in kv_dpm_enable()
1365 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1367 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1376 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1378 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1399 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); in kv_dpm_disable()
1497 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1533 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
1549 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_update_vce_dpm()
1596 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_update_samu_dpm()
1627 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_get_acp_boot_level()
1660 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_update_acp_dpm()
1808 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
1928 adev->pm.dpm.forced_level = level; in kv_dpm_force_performance_level()
1936 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in kv_dpm_pre_set_power_state()
1956 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.dpm.ac_power); in kv_dpm_set_power_state()
2081 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_patch_voltage_values()
2083 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_patch_voltage_values()
2085 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_patch_voltage_values()
2087 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_patch_voltage_values()
2201 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2242 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2245 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_apply_state_adjust_rules()
2248 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()
2249 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2275 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in kv_apply_state_adjust_rules()
2276 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in kv_apply_state_adjust_rules()
2337 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2379 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_calculate_nbps_level_settings()
2396 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2446 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
2570 adev->pm.dpm.thermal.min_temp = low_temp; in kv_set_thermal_temperature_range()
2571 adev->pm.dpm.thermal.max_temp = high_temp; in kv_set_thermal_temperature_range()
2644 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in kv_parse_sys_info_table()
2699 adev->pm.dpm.boot_ps = rps; in kv_parse_pplib_non_clock_info()
2703 adev->pm.dpm.uvd_ps = rps; in kv_parse_pplib_non_clock_info()
2762 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) * in kv_parse_power_table()
2764 if (!adev->pm.dpm.ps) in kv_parse_power_table()
2775 kfree(adev->pm.dpm.ps); in kv_parse_power_table()
2778 adev->pm.dpm.ps[i].ps_priv = ps; in kv_parse_power_table()
2791 &adev->pm.dpm.ps[i], k, in kv_parse_power_table()
2795 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in kv_parse_power_table()
2800 adev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
2805 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in kv_parse_power_table()
2810 adev->pm.dpm.vce_states[i].sclk = sclk; in kv_parse_power_table()
2811 adev->pm.dpm.vce_states[i].mclk = 0; in kv_parse_power_table()
2825 adev->pm.dpm.priv = pi; in kv_dpm_init()
2935 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in kv_dpm_fini()
2936 kfree(adev->pm.dpm.ps[i].ps_priv); in kv_dpm_fini()
2938 kfree(adev->pm.dpm.ps); in kv_dpm_fini()
2939 kfree(adev->pm.dpm.priv); in kv_dpm_fini()
3021 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
3025 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
3030 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3031 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3032 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO; in kv_dpm_sw_init()
3042 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in kv_dpm_sw_init()
3047 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_sw_init()
3113 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_suspend()
3272 adev->pm.dpm.thermal.high_to_low = false; in kv_dpm_process_interrupt()
3277 adev->pm.dpm.thermal.high_to_low = true; in kv_dpm_process_interrupt()
3285 schedule_work(&adev->pm.dpm.thermal.work); in kv_dpm_process_interrupt()
3347 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in kv_dpm_set_irq_funcs()
3348 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; in kv_dpm_set_irq_funcs()