Lines Matching refs:adev
45 static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev);
46 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
47 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
49 static void kv_init_graphics_levels(struct amdgpu_device *adev);
50 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
51 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
52 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
53 static void kv_enable_new_levels(struct amdgpu_device *adev);
54 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
56 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
57 static int kv_set_enabled_levels(struct amdgpu_device *adev);
58 static int kv_force_dpm_highest(struct amdgpu_device *adev);
59 static int kv_force_dpm_lowest(struct amdgpu_device *adev);
60 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
63 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
65 static int kv_init_fps_limits(struct amdgpu_device *adev);
67 static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
68 static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
69 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
70 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
73 static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev, in kv_convert_vid2_to_vid7() argument
78 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
95 static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev, in kv_convert_vid7_to_vid2() argument
100 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
119 static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable) in sumo_take_smu_control() argument
143 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev, in sumo_construct_sclk_voltage_mapping_table() argument
165 static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev, in sumo_construct_vid_mapping_table() argument
382 static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev) in kv_get_pi() argument
384 struct kv_power_info *pi = adev->pm.dpm.priv; in kv_get_pi()
390 static void kv_program_local_cac_table(struct amdgpu_device *adev,
415 static int kv_program_pt_config_registers(struct amdgpu_device *adev, in kv_program_pt_config_registers() argument
464 static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable) in kv_do_enable_didt() argument
466 struct kv_power_info *pi = kv_get_pi(adev); in kv_do_enable_didt()
506 static int kv_enable_didt(struct amdgpu_device *adev, bool enable) in kv_enable_didt() argument
508 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_didt()
515 gfx_v7_0_enter_rlc_safe_mode(adev); in kv_enable_didt()
518 ret = kv_program_pt_config_registers(adev, didt_config_kv); in kv_enable_didt()
520 gfx_v7_0_exit_rlc_safe_mode(adev); in kv_enable_didt()
525 kv_do_enable_didt(adev, enable); in kv_enable_didt()
527 gfx_v7_0_exit_rlc_safe_mode(adev); in kv_enable_didt()
534 static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
536 struct kv_power_info *pi = kv_get_pi(adev);
541 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
545 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
549 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
553 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
557 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
561 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
566 static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable) in kv_enable_smc_cac() argument
568 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_smc_cac()
573 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac); in kv_enable_smc_cac()
579 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac); in kv_enable_smc_cac()
587 static int kv_process_firmware_header(struct amdgpu_device *adev) in kv_process_firmware_header() argument
589 struct kv_power_info *pi = kv_get_pi(adev); in kv_process_firmware_header()
593 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + in kv_process_firmware_header()
600 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + in kv_process_firmware_header()
610 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev) in kv_enable_dpm_voltage_scaling() argument
612 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_dpm_voltage_scaling()
617 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_enable_dpm_voltage_scaling()
626 static int kv_set_dpm_interval(struct amdgpu_device *adev) in kv_set_dpm_interval() argument
628 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_interval()
633 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_set_dpm_interval()
642 static int kv_set_dpm_boot_state(struct amdgpu_device *adev) in kv_set_dpm_boot_state() argument
644 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_dpm_boot_state()
647 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_set_dpm_boot_state()
656 static void kv_program_vc(struct amdgpu_device *adev) in kv_program_vc() argument
661 static void kv_clear_vc(struct amdgpu_device *adev) in kv_clear_vc() argument
666 static int kv_set_divider_value(struct amdgpu_device *adev, in kv_set_divider_value() argument
669 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_divider_value()
673 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_set_divider_value()
684 static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev, in kv_convert_8bit_index_to_voltage() argument
690 static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev, in kv_convert_2bit_index_to_voltage() argument
693 struct kv_power_info *pi = kv_get_pi(adev); in kv_convert_2bit_index_to_voltage()
694 u32 vid_8bit = kv_convert_vid2_to_vid7(adev, in kv_convert_2bit_index_to_voltage()
698 return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit); in kv_convert_2bit_index_to_voltage()
702 static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid) in kv_set_vid() argument
704 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_vid()
708 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid)); in kv_set_vid()
713 static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at) in kv_set_at() argument
715 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_at()
722 static void kv_dpm_power_level_enable(struct amdgpu_device *adev, in kv_dpm_power_level_enable() argument
725 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enable()
730 static void kv_start_dpm(struct amdgpu_device *adev) in kv_start_dpm() argument
737 amdgpu_kv_smc_dpm_enable(adev, true); in kv_start_dpm()
740 static void kv_stop_dpm(struct amdgpu_device *adev) in kv_stop_dpm() argument
742 amdgpu_kv_smc_dpm_enable(adev, false); in kv_stop_dpm()
745 static void kv_start_am(struct amdgpu_device *adev) in kv_start_am() argument
756 static void kv_reset_am(struct amdgpu_device *adev) in kv_reset_am() argument
766 static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze) in kv_freeze_sclk_dpm() argument
768 return amdgpu_kv_notify_message_to_smu(adev, freeze ? in kv_freeze_sclk_dpm()
772 static int kv_force_lowest_valid(struct amdgpu_device *adev) in kv_force_lowest_valid() argument
774 return kv_force_dpm_lowest(adev); in kv_force_lowest_valid()
777 static int kv_unforce_levels(struct amdgpu_device *adev) in kv_unforce_levels() argument
779 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_unforce_levels()
780 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel); in kv_unforce_levels()
782 return kv_set_enabled_levels(adev); in kv_unforce_levels()
785 static int kv_update_sclk_t(struct amdgpu_device *adev) in kv_update_sclk_t() argument
787 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_sclk_t()
794 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_sclk_t()
803 static int kv_program_bootup_state(struct amdgpu_device *adev) in kv_program_bootup_state() argument
805 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_bootup_state()
808 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
817 kv_dpm_power_level_enable(adev, i, true); in kv_program_bootup_state()
831 kv_dpm_power_level_enable(adev, i, true); in kv_program_bootup_state()
836 static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev) in kv_enable_auto_thermal_throttling() argument
838 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_auto_thermal_throttling()
843 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_enable_auto_thermal_throttling()
852 static int kv_upload_dpm_settings(struct amdgpu_device *adev) in kv_upload_dpm_settings() argument
854 struct kv_power_info *pi = kv_get_pi(adev); in kv_upload_dpm_settings()
857 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_upload_dpm_settings()
867 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_upload_dpm_settings()
881 static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk) in kv_get_clk_bypass() argument
883 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_clk_bypass()
906 static int kv_populate_uvd_table(struct amdgpu_device *adev) in kv_populate_uvd_table() argument
908 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_uvd_table()
910 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
929 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk); in kv_populate_uvd_table()
931 (u8)kv_get_clk_bypass(adev, table->entries[i].dclk); in kv_populate_uvd_table()
933 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_uvd_table()
939 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_uvd_table()
948 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
958 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
966 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_uvd_table()
977 static int kv_populate_vce_table(struct amdgpu_device *adev) in kv_populate_vce_table() argument
979 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_vce_table()
983 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
999 (u8)kv_get_clk_bypass(adev, table->entries[i].evclk); in kv_populate_vce_table()
1001 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_vce_table()
1010 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1021 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1030 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_vce_table()
1040 static int kv_populate_samu_table(struct amdgpu_device *adev) in kv_populate_samu_table() argument
1042 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_samu_table()
1044 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1062 (u8)kv_get_clk_bypass(adev, table->entries[i].clk); in kv_populate_samu_table()
1064 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_samu_table()
1073 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1084 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1093 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_samu_table()
1106 static int kv_populate_acp_table(struct amdgpu_device *adev) in kv_populate_acp_table() argument
1108 struct kv_power_info *pi = kv_get_pi(adev); in kv_populate_acp_table()
1110 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1123 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, in kv_populate_acp_table()
1132 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1143 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1152 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_populate_acp_table()
1164 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev) in kv_calculate_dfs_bypass_settings() argument
1166 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dfs_bypass_settings()
1169 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1214 static int kv_enable_ulv(struct amdgpu_device *adev, bool enable) in kv_enable_ulv() argument
1216 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_ulv()
1220 static void kv_reset_acp_boot_level(struct amdgpu_device *adev) in kv_reset_acp_boot_level() argument
1222 struct kv_power_info *pi = kv_get_pi(adev); in kv_reset_acp_boot_level()
1227 static void kv_update_current_ps(struct amdgpu_device *adev, in kv_update_current_ps() argument
1231 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_current_ps()
1238 static void kv_update_requested_ps(struct amdgpu_device *adev, in kv_update_requested_ps() argument
1242 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_requested_ps()
1249 static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable) in kv_dpm_enable_bapm() argument
1251 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable_bapm()
1255 ret = amdgpu_kv_smc_bapm_enable(adev, enable); in kv_dpm_enable_bapm()
1261 static int kv_dpm_enable(struct amdgpu_device *adev) in kv_dpm_enable() argument
1263 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_enable()
1266 ret = kv_process_firmware_header(adev); in kv_dpm_enable()
1271 kv_init_fps_limits(adev); in kv_dpm_enable()
1272 kv_init_graphics_levels(adev); in kv_dpm_enable()
1273 ret = kv_program_bootup_state(adev); in kv_dpm_enable()
1278 kv_calculate_dfs_bypass_settings(adev); in kv_dpm_enable()
1279 ret = kv_upload_dpm_settings(adev); in kv_dpm_enable()
1284 ret = kv_populate_uvd_table(adev); in kv_dpm_enable()
1289 ret = kv_populate_vce_table(adev); in kv_dpm_enable()
1294 ret = kv_populate_samu_table(adev); in kv_dpm_enable()
1299 ret = kv_populate_acp_table(adev); in kv_dpm_enable()
1304 kv_program_vc(adev); in kv_dpm_enable()
1306 kv_initialize_hardware_cac_manager(adev); in kv_dpm_enable()
1308 kv_start_am(adev); in kv_dpm_enable()
1310 ret = kv_enable_auto_thermal_throttling(adev); in kv_dpm_enable()
1316 ret = kv_enable_dpm_voltage_scaling(adev); in kv_dpm_enable()
1321 ret = kv_set_dpm_interval(adev); in kv_dpm_enable()
1326 ret = kv_set_dpm_boot_state(adev); in kv_dpm_enable()
1331 ret = kv_enable_ulv(adev, true); in kv_dpm_enable()
1336 kv_start_dpm(adev); in kv_dpm_enable()
1337 ret = kv_enable_didt(adev, true); in kv_dpm_enable()
1342 ret = kv_enable_smc_cac(adev, true); in kv_dpm_enable()
1348 kv_reset_acp_boot_level(adev); in kv_dpm_enable()
1350 ret = amdgpu_kv_smc_bapm_enable(adev, false); in kv_dpm_enable()
1356 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); in kv_dpm_enable()
1358 if (adev->irq.installed && in kv_dpm_enable()
1359 amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) { in kv_dpm_enable()
1360 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX); in kv_dpm_enable()
1365 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1367 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_enable()
1374 static void kv_dpm_disable(struct amdgpu_device *adev) in kv_dpm_disable() argument
1376 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1378 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, in kv_dpm_disable()
1381 amdgpu_kv_smc_bapm_enable(adev, false); in kv_dpm_disable()
1383 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_disable()
1384 kv_enable_nb_dpm(adev, false); in kv_dpm_disable()
1387 kv_dpm_powergate_acp(adev, false); in kv_dpm_disable()
1388 kv_dpm_powergate_samu(adev, false); in kv_dpm_disable()
1389 kv_dpm_powergate_vce(adev, false); in kv_dpm_disable()
1390 kv_dpm_powergate_uvd(adev, false); in kv_dpm_disable()
1392 kv_enable_smc_cac(adev, false); in kv_dpm_disable()
1393 kv_enable_didt(adev, false); in kv_dpm_disable()
1394 kv_clear_vc(adev); in kv_dpm_disable()
1395 kv_stop_dpm(adev); in kv_dpm_disable()
1396 kv_enable_ulv(adev, false); in kv_dpm_disable()
1397 kv_reset_am(adev); in kv_dpm_disable()
1399 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); in kv_dpm_disable()
1403 static int kv_write_smc_soft_register(struct amdgpu_device *adev,
1406 struct kv_power_info *pi = kv_get_pi(adev);
1408 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1412 static int kv_read_smc_soft_register(struct amdgpu_device *adev,
1415 struct kv_power_info *pi = kv_get_pi(adev);
1417 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1422 static void kv_init_sclk_t(struct amdgpu_device *adev) in kv_init_sclk_t() argument
1424 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_sclk_t()
1429 static int kv_init_fps_limits(struct amdgpu_device *adev) in kv_init_fps_limits() argument
1431 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_fps_limits()
1439 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_init_fps_limits()
1448 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_init_fps_limits()
1458 static void kv_init_powergate_state(struct amdgpu_device *adev) in kv_init_powergate_state() argument
1460 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_powergate_state()
1469 static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_uvd_dpm() argument
1471 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_uvd_dpm()
1475 static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_vce_dpm() argument
1477 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_vce_dpm()
1481 static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_samu_dpm() argument
1483 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_samu_dpm()
1487 static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable) in kv_enable_acp_dpm() argument
1489 return amdgpu_kv_notify_message_to_smu(adev, enable ? in kv_enable_acp_dpm()
1493 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate) in kv_update_uvd_dpm() argument
1495 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_uvd_dpm()
1497 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1513 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_uvd_dpm()
1521 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_uvd_dpm()
1526 return kv_enable_uvd_dpm(adev, !gate); in kv_update_uvd_dpm()
1529 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk) in kv_get_vce_boot_level() argument
1533 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
1543 static int kv_update_vce_dpm(struct amdgpu_device *adev, in kv_update_vce_dpm() argument
1547 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_vce_dpm()
1549 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_update_vce_dpm()
1553 kv_dpm_powergate_vce(adev, false); in kv_update_vce_dpm()
1555 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in kv_update_vce_dpm()
1562 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); in kv_update_vce_dpm()
1564 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_vce_dpm()
1574 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_vce_dpm()
1578 kv_enable_vce_dpm(adev, true); in kv_update_vce_dpm()
1580 kv_enable_vce_dpm(adev, false); in kv_update_vce_dpm()
1582 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in kv_update_vce_dpm()
1586 kv_dpm_powergate_vce(adev, true); in kv_update_vce_dpm()
1592 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate) in kv_update_samu_dpm() argument
1594 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_samu_dpm()
1596 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_update_samu_dpm()
1605 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_samu_dpm()
1615 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_samu_dpm()
1620 return kv_enable_samu_dpm(adev, !gate); in kv_update_samu_dpm()
1623 static u8 kv_get_acp_boot_level(struct amdgpu_device *adev) in kv_get_acp_boot_level() argument
1627 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_get_acp_boot_level()
1640 static void kv_update_acp_boot_level(struct amdgpu_device *adev) in kv_update_acp_boot_level() argument
1642 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_boot_level()
1646 acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_boot_level()
1649 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_acp_boot_level()
1656 static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate) in kv_update_acp_dpm() argument
1658 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_acp_dpm()
1660 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_update_acp_dpm()
1667 pi->acp_boot_level = kv_get_acp_boot_level(adev); in kv_update_acp_dpm()
1669 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_acp_dpm()
1679 amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_update_acp_dpm()
1684 return kv_enable_acp_dpm(adev, !gate); in kv_update_acp_dpm()
1687 static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) in kv_dpm_powergate_uvd() argument
1689 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_uvd()
1700 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in kv_dpm_powergate_uvd()
1703 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in kv_dpm_powergate_uvd()
1707 kv_update_uvd_dpm(adev, gate); in kv_dpm_powergate_uvd()
1710 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF); in kv_dpm_powergate_uvd()
1714 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); in kv_dpm_powergate_uvd()
1716 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in kv_dpm_powergate_uvd()
1719 ret = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, in kv_dpm_powergate_uvd()
1723 kv_update_uvd_dpm(adev, gate); in kv_dpm_powergate_uvd()
1727 static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate) in kv_dpm_powergate_vce() argument
1729 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_vce()
1740 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in kv_dpm_powergate_vce()
1744 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF); in kv_dpm_powergate_vce()
1749 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); in kv_dpm_powergate_vce()
1751 ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, in kv_dpm_powergate_vce()
1758 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate) in kv_dpm_powergate_samu() argument
1760 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_samu()
1768 kv_update_samu_dpm(adev, true); in kv_dpm_powergate_samu()
1770 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF); in kv_dpm_powergate_samu()
1773 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON); in kv_dpm_powergate_samu()
1774 kv_update_samu_dpm(adev, false); in kv_dpm_powergate_samu()
1778 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate) in kv_dpm_powergate_acp() argument
1780 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_powergate_acp()
1785 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_dpm_powergate_acp()
1791 kv_update_acp_dpm(adev, true); in kv_dpm_powergate_acp()
1793 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF); in kv_dpm_powergate_acp()
1796 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON); in kv_dpm_powergate_acp()
1797 kv_update_acp_dpm(adev, false); in kv_dpm_powergate_acp()
1801 static void kv_set_valid_clock_range(struct amdgpu_device *adev, in kv_set_valid_clock_range() argument
1805 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_valid_clock_range()
1808 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_set_valid_clock_range()
1863 static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev, in kv_update_dfs_bypass_settings() argument
1867 struct kv_power_info *pi = kv_get_pi(adev); in kv_update_dfs_bypass_settings()
1874 ret = amdgpu_kv_copy_bytes_to_smc(adev, in kv_update_dfs_bypass_settings()
1886 static int kv_enable_nb_dpm(struct amdgpu_device *adev, in kv_enable_nb_dpm() argument
1889 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_nb_dpm()
1894 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable); in kv_enable_nb_dpm()
1900 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable); in kv_enable_nb_dpm()
1909 static int kv_dpm_force_performance_level(struct amdgpu_device *adev, in kv_dpm_force_performance_level() argument
1915 ret = kv_force_dpm_highest(adev); in kv_dpm_force_performance_level()
1919 ret = kv_force_dpm_lowest(adev); in kv_dpm_force_performance_level()
1923 ret = kv_unforce_levels(adev); in kv_dpm_force_performance_level()
1928 adev->pm.dpm.forced_level = level; in kv_dpm_force_performance_level()
1933 static int kv_dpm_pre_set_power_state(struct amdgpu_device *adev) in kv_dpm_pre_set_power_state() argument
1935 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_pre_set_power_state()
1936 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; in kv_dpm_pre_set_power_state()
1939 kv_update_requested_ps(adev, new_ps); in kv_dpm_pre_set_power_state()
1941 kv_apply_state_adjust_rules(adev, in kv_dpm_pre_set_power_state()
1948 static int kv_dpm_set_power_state(struct amdgpu_device *adev) in kv_dpm_set_power_state() argument
1950 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_set_power_state()
1956 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.dpm.ac_power); in kv_dpm_set_power_state()
1963 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_dpm_set_power_state()
1965 kv_set_valid_clock_range(adev, new_ps); in kv_dpm_set_power_state()
1966 kv_update_dfs_bypass_settings(adev, new_ps); in kv_dpm_set_power_state()
1967 ret = kv_calculate_ds_divider(adev); in kv_dpm_set_power_state()
1972 kv_calculate_nbps_level_settings(adev); in kv_dpm_set_power_state()
1973 kv_calculate_dpm_settings(adev); in kv_dpm_set_power_state()
1974 kv_force_lowest_valid(adev); in kv_dpm_set_power_state()
1975 kv_enable_new_levels(adev); in kv_dpm_set_power_state()
1976 kv_upload_dpm_settings(adev); in kv_dpm_set_power_state()
1977 kv_program_nbps_index_settings(adev, new_ps); in kv_dpm_set_power_state()
1978 kv_unforce_levels(adev); in kv_dpm_set_power_state()
1979 kv_set_enabled_levels(adev); in kv_dpm_set_power_state()
1980 kv_force_lowest_valid(adev); in kv_dpm_set_power_state()
1981 kv_unforce_levels(adev); in kv_dpm_set_power_state()
1983 ret = kv_update_vce_dpm(adev, new_ps, old_ps); in kv_dpm_set_power_state()
1988 kv_update_sclk_t(adev); in kv_dpm_set_power_state()
1989 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_set_power_state()
1990 kv_enable_nb_dpm(adev, true); in kv_dpm_set_power_state()
1994 kv_set_valid_clock_range(adev, new_ps); in kv_dpm_set_power_state()
1995 kv_update_dfs_bypass_settings(adev, new_ps); in kv_dpm_set_power_state()
1996 ret = kv_calculate_ds_divider(adev); in kv_dpm_set_power_state()
2001 kv_calculate_nbps_level_settings(adev); in kv_dpm_set_power_state()
2002 kv_calculate_dpm_settings(adev); in kv_dpm_set_power_state()
2003 kv_freeze_sclk_dpm(adev, true); in kv_dpm_set_power_state()
2004 kv_upload_dpm_settings(adev); in kv_dpm_set_power_state()
2005 kv_program_nbps_index_settings(adev, new_ps); in kv_dpm_set_power_state()
2006 kv_freeze_sclk_dpm(adev, false); in kv_dpm_set_power_state()
2007 kv_set_enabled_levels(adev); in kv_dpm_set_power_state()
2008 ret = kv_update_vce_dpm(adev, new_ps, old_ps); in kv_dpm_set_power_state()
2013 kv_update_acp_boot_level(adev); in kv_dpm_set_power_state()
2014 kv_update_sclk_t(adev); in kv_dpm_set_power_state()
2015 kv_enable_nb_dpm(adev, true); in kv_dpm_set_power_state()
2022 static void kv_dpm_post_set_power_state(struct amdgpu_device *adev) in kv_dpm_post_set_power_state() argument
2024 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_post_set_power_state()
2027 kv_update_current_ps(adev, new_ps); in kv_dpm_post_set_power_state()
2030 static void kv_dpm_setup_asic(struct amdgpu_device *adev) in kv_dpm_setup_asic() argument
2032 sumo_take_smu_control(adev, true); in kv_dpm_setup_asic()
2033 kv_init_powergate_state(adev); in kv_dpm_setup_asic()
2034 kv_init_sclk_t(adev); in kv_dpm_setup_asic()
2038 static void kv_dpm_reset_asic(struct amdgpu_device *adev)
2040 struct kv_power_info *pi = kv_get_pi(adev);
2042 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2043 kv_force_lowest_valid(adev);
2044 kv_init_graphics_levels(adev);
2045 kv_program_bootup_state(adev);
2046 kv_upload_dpm_settings(adev);
2047 kv_force_lowest_valid(adev);
2048 kv_unforce_levels(adev);
2050 kv_init_graphics_levels(adev);
2051 kv_program_bootup_state(adev);
2052 kv_freeze_sclk_dpm(adev, true);
2053 kv_upload_dpm_settings(adev);
2054 kv_freeze_sclk_dpm(adev, false);
2055 kv_set_enabled_level(adev, pi->graphics_boot_level);
2060 static void kv_construct_max_power_limits_table(struct amdgpu_device *adev, in kv_construct_max_power_limits_table() argument
2063 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_max_power_limits_table()
2070 kv_convert_2bit_index_to_voltage(adev, in kv_construct_max_power_limits_table()
2077 static void kv_patch_voltage_values(struct amdgpu_device *adev) in kv_patch_voltage_values() argument
2081 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_patch_voltage_values()
2083 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_patch_voltage_values()
2085 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_patch_voltage_values()
2087 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_patch_voltage_values()
2092 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2099 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2106 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2113 kv_convert_8bit_index_to_voltage(adev, in kv_patch_voltage_values()
2119 static void kv_construct_boot_state(struct amdgpu_device *adev) in kv_construct_boot_state() argument
2121 struct kv_power_info *pi = kv_get_pi(adev); in kv_construct_boot_state()
2133 static int kv_force_dpm_highest(struct amdgpu_device *adev) in kv_force_dpm_highest() argument
2138 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); in kv_force_dpm_highest()
2147 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_highest()
2148 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); in kv_force_dpm_highest()
2150 return kv_set_enabled_level(adev, i); in kv_force_dpm_highest()
2153 static int kv_force_dpm_lowest(struct amdgpu_device *adev) in kv_force_dpm_lowest() argument
2158 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); in kv_force_dpm_lowest()
2167 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_lowest()
2168 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); in kv_force_dpm_lowest()
2170 return kv_set_enabled_level(adev, i); in kv_force_dpm_lowest()
2173 static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, in kv_get_sleep_divider_id_from_clock() argument
2176 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_sleep_divider_id_from_clock()
2197 static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit) in kv_get_high_voltage_limit() argument
2199 struct kv_power_info *pi = kv_get_pi(adev); in kv_get_high_voltage_limit()
2201 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_get_high_voltage_limit()
2207 (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <= in kv_get_high_voltage_limit()
2219 (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <= in kv_get_high_voltage_limit()
2231 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev, in kv_apply_state_adjust_rules() argument
2236 struct kv_power_info *pi = kv_get_pi(adev); in kv_apply_state_adjust_rules()
2242 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_apply_state_adjust_rules()
2245 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_apply_state_adjust_rules()
2248 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in kv_apply_state_adjust_rules()
2249 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2275 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) in kv_apply_state_adjust_rules()
2276 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; in kv_apply_state_adjust_rules()
2290 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { in kv_apply_state_adjust_rules()
2291 kv_get_high_voltage_limit(adev, &limit); in kv_apply_state_adjust_rules()
2302 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { in kv_apply_state_adjust_rules()
2303 kv_get_high_voltage_limit(adev, &limit); in kv_apply_state_adjust_rules()
2324 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_apply_state_adjust_rules()
2337 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2347 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev, in kv_dpm_power_level_enabled_for_throttle() argument
2350 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_power_level_enabled_for_throttle()
2355 static int kv_calculate_ds_divider(struct amdgpu_device *adev) in kv_calculate_ds_divider() argument
2357 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_ds_divider()
2366 kv_get_sleep_divider_id_from_clock(adev, in kv_calculate_ds_divider()
2373 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev) in kv_calculate_nbps_level_settings() argument
2375 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_nbps_level_settings()
2379 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in kv_calculate_nbps_level_settings()
2385 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_calculate_nbps_level_settings()
2396 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2427 static int kv_calculate_dpm_settings(struct amdgpu_device *adev) in kv_calculate_dpm_settings() argument
2429 struct kv_power_info *pi = kv_get_pi(adev); in kv_calculate_dpm_settings()
2441 static void kv_init_graphics_levels(struct amdgpu_device *adev) in kv_init_graphics_levels() argument
2443 struct kv_power_info *pi = kv_get_pi(adev); in kv_init_graphics_levels()
2446 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_init_graphics_levels()
2455 kv_convert_8bit_index_to_voltage(adev, table->entries[i].v))) in kv_init_graphics_levels()
2458 kv_set_divider_value(adev, i, table->entries[i].clk); in kv_init_graphics_levels()
2459 vid_2bit = kv_convert_vid7_to_vid2(adev, in kv_init_graphics_levels()
2462 kv_set_vid(adev, i, vid_2bit); in kv_init_graphics_levels()
2463 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2464 kv_dpm_power_level_enabled_for_throttle(adev, i, true); in kv_init_graphics_levels()
2475 kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit)) in kv_init_graphics_levels()
2478 kv_set_divider_value(adev, i, table->entries[i].sclk_frequency); in kv_init_graphics_levels()
2479 kv_set_vid(adev, i, table->entries[i].vid_2bit); in kv_init_graphics_levels()
2480 kv_set_at(adev, i, pi->at[i]); in kv_init_graphics_levels()
2481 kv_dpm_power_level_enabled_for_throttle(adev, i, true); in kv_init_graphics_levels()
2487 kv_dpm_power_level_enable(adev, i, false); in kv_init_graphics_levels()
2490 static void kv_enable_new_levels(struct amdgpu_device *adev) in kv_enable_new_levels() argument
2492 struct kv_power_info *pi = kv_get_pi(adev); in kv_enable_new_levels()
2497 kv_dpm_power_level_enable(adev, i, true); in kv_enable_new_levels()
2501 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level) in kv_set_enabled_level() argument
2505 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_set_enabled_level()
2510 static int kv_set_enabled_levels(struct amdgpu_device *adev) in kv_set_enabled_levels() argument
2512 struct kv_power_info *pi = kv_get_pi(adev); in kv_set_enabled_levels()
2518 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, in kv_set_enabled_levels()
2523 static void kv_program_nbps_index_settings(struct amdgpu_device *adev, in kv_program_nbps_index_settings() argument
2527 struct kv_power_info *pi = kv_get_pi(adev); in kv_program_nbps_index_settings()
2530 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_program_nbps_index_settings()
2547 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev, in kv_set_thermal_temperature_range() argument
2570 adev->pm.dpm.thermal.min_temp = low_temp; in kv_set_thermal_temperature_range()
2571 adev->pm.dpm.thermal.max_temp = high_temp; in kv_set_thermal_temperature_range()
2585 static int kv_parse_sys_info_table(struct amdgpu_device *adev) in kv_parse_sys_info_table() argument
2587 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_sys_info_table()
2588 struct amdgpu_mode_info *mode_info = &adev->mode_info; in kv_parse_sys_info_table()
2635 sumo_construct_sclk_voltage_mapping_table(adev, in kv_parse_sys_info_table()
2639 sumo_construct_vid_mapping_table(adev, in kv_parse_sys_info_table()
2643 kv_construct_max_power_limits_table(adev, in kv_parse_sys_info_table()
2644 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in kv_parse_sys_info_table()
2670 static void kv_patch_boot_state(struct amdgpu_device *adev, in kv_patch_boot_state() argument
2673 struct kv_power_info *pi = kv_get_pi(adev); in kv_patch_boot_state()
2679 static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev, in kv_parse_pplib_non_clock_info() argument
2699 adev->pm.dpm.boot_ps = rps; in kv_parse_pplib_non_clock_info()
2700 kv_patch_boot_state(adev, ps); in kv_parse_pplib_non_clock_info()
2703 adev->pm.dpm.uvd_ps = rps; in kv_parse_pplib_non_clock_info()
2706 static void kv_parse_pplib_clock_info(struct amdgpu_device *adev, in kv_parse_pplib_clock_info() argument
2710 struct kv_power_info *pi = kv_get_pi(adev); in kv_parse_pplib_clock_info()
2728 static int kv_parse_power_table(struct amdgpu_device *adev) in kv_parse_power_table() argument
2730 struct amdgpu_mode_info *mode_info = &adev->mode_info; in kv_parse_power_table()
2750 amdgpu_add_thermal_controller(adev); in kv_parse_power_table()
2762 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) * in kv_parse_power_table()
2764 if (!adev->pm.dpm.ps) in kv_parse_power_table()
2775 kfree(adev->pm.dpm.ps); in kv_parse_power_table()
2778 adev->pm.dpm.ps[i].ps_priv = ps; in kv_parse_power_table()
2790 kv_parse_pplib_clock_info(adev, in kv_parse_power_table()
2791 &adev->pm.dpm.ps[i], k, in kv_parse_power_table()
2795 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], in kv_parse_power_table()
2800 adev->pm.dpm.num_ps = state_array->ucNumEntries; in kv_parse_power_table()
2805 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; in kv_parse_power_table()
2810 adev->pm.dpm.vce_states[i].sclk = sclk; in kv_parse_power_table()
2811 adev->pm.dpm.vce_states[i].mclk = 0; in kv_parse_power_table()
2817 static int kv_dpm_init(struct amdgpu_device *adev) in kv_dpm_init() argument
2825 adev->pm.dpm.priv = pi; in kv_dpm_init()
2827 ret = amdgpu_get_platform_caps(adev); in kv_dpm_init()
2831 ret = amdgpu_parse_extended_power_table(adev); in kv_dpm_init()
2862 pi->caps_uvd_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_UVD) ? true : false; in kv_dpm_init()
2864 pi->caps_vce_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_VCE) ? true : false; in kv_dpm_init()
2865 pi->caps_samu_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_SAMU) ? true : false; in kv_dpm_init()
2866 pi->caps_acp_pg = (adev->pg_flags & AMDGPU_PG_SUPPORT_ACP) ? true : false; in kv_dpm_init()
2869 ret = kv_parse_sys_info_table(adev); in kv_dpm_init()
2873 kv_patch_voltage_values(adev); in kv_dpm_init()
2874 kv_construct_boot_state(adev); in kv_dpm_init()
2876 ret = kv_parse_power_table(adev); in kv_dpm_init()
2886 kv_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, in kv_dpm_debugfs_print_current_performance_level() argument
2889 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_debugfs_print_current_performance_level()
2904 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp); in kv_dpm_debugfs_print_current_performance_level()
2913 kv_dpm_print_power_state(struct amdgpu_device *adev, in kv_dpm_print_power_state() argument
2926 kv_convert_8bit_index_to_voltage(adev, pl->vddc_index)); in kv_dpm_print_power_state()
2928 amdgpu_dpm_print_ps_status(adev, rps); in kv_dpm_print_power_state()
2931 static void kv_dpm_fini(struct amdgpu_device *adev) in kv_dpm_fini() argument
2935 for (i = 0; i < adev->pm.dpm.num_ps; i++) { in kv_dpm_fini()
2936 kfree(adev->pm.dpm.ps[i].ps_priv); in kv_dpm_fini()
2938 kfree(adev->pm.dpm.ps); in kv_dpm_fini()
2939 kfree(adev->pm.dpm.priv); in kv_dpm_fini()
2940 amdgpu_free_extended_power_table(adev); in kv_dpm_fini()
2943 static void kv_dpm_display_configuration_changed(struct amdgpu_device *adev) in kv_dpm_display_configuration_changed() argument
2948 static u32 kv_dpm_get_sclk(struct amdgpu_device *adev, bool low) in kv_dpm_get_sclk() argument
2950 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_sclk()
2959 static u32 kv_dpm_get_mclk(struct amdgpu_device *adev, bool low) in kv_dpm_get_mclk() argument
2961 struct kv_power_info *pi = kv_get_pi(adev); in kv_dpm_get_mclk()
2967 static int kv_dpm_get_temp(struct amdgpu_device *adev) in kv_dpm_get_temp() argument
2986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_early_init() local
2988 kv_dpm_set_dpm_funcs(adev); in kv_dpm_early_init()
2989 kv_dpm_set_irq_funcs(adev); in kv_dpm_early_init()
2997 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_late_init() local
3004 ret = amdgpu_pm_sysfs_init(adev); in kv_dpm_late_init()
3008 kv_dpm_powergate_acp(adev, true); in kv_dpm_late_init()
3009 kv_dpm_powergate_samu(adev, true); in kv_dpm_late_init()
3010 kv_dpm_powergate_vce(adev, true); in kv_dpm_late_init()
3011 kv_dpm_powergate_uvd(adev, true); in kv_dpm_late_init()
3019 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_sw_init() local
3021 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
3025 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq); in kv_dpm_sw_init()
3030 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3031 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; in kv_dpm_sw_init()
3032 adev->pm.dpm.forced_level = AMDGPU_DPM_FORCED_LEVEL_AUTO; in kv_dpm_sw_init()
3033 adev->pm.default_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
3034 adev->pm.default_mclk = adev->clock.default_mclk; in kv_dpm_sw_init()
3035 adev->pm.current_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
3036 adev->pm.current_mclk = adev->clock.default_mclk; in kv_dpm_sw_init()
3037 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; in kv_dpm_sw_init()
3042 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); in kv_dpm_sw_init()
3043 mutex_lock(&adev->pm.mutex); in kv_dpm_sw_init()
3044 ret = kv_dpm_init(adev); in kv_dpm_sw_init()
3047 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_sw_init()
3049 amdgpu_pm_print_power_states(adev); in kv_dpm_sw_init()
3050 mutex_unlock(&adev->pm.mutex); in kv_dpm_sw_init()
3056 kv_dpm_fini(adev); in kv_dpm_sw_init()
3057 mutex_unlock(&adev->pm.mutex); in kv_dpm_sw_init()
3064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_sw_fini() local
3066 mutex_lock(&adev->pm.mutex); in kv_dpm_sw_fini()
3067 amdgpu_pm_sysfs_fini(adev); in kv_dpm_sw_fini()
3068 kv_dpm_fini(adev); in kv_dpm_sw_fini()
3069 mutex_unlock(&adev->pm.mutex); in kv_dpm_sw_fini()
3077 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_hw_init() local
3079 mutex_lock(&adev->pm.mutex); in kv_dpm_hw_init()
3080 kv_dpm_setup_asic(adev); in kv_dpm_hw_init()
3081 ret = kv_dpm_enable(adev); in kv_dpm_hw_init()
3083 adev->pm.dpm_enabled = false; in kv_dpm_hw_init()
3085 adev->pm.dpm_enabled = true; in kv_dpm_hw_init()
3086 mutex_unlock(&adev->pm.mutex); in kv_dpm_hw_init()
3093 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_hw_fini() local
3095 if (adev->pm.dpm_enabled) { in kv_dpm_hw_fini()
3096 mutex_lock(&adev->pm.mutex); in kv_dpm_hw_fini()
3097 kv_dpm_disable(adev); in kv_dpm_hw_fini()
3098 mutex_unlock(&adev->pm.mutex); in kv_dpm_hw_fini()
3106 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_suspend() local
3108 if (adev->pm.dpm_enabled) { in kv_dpm_suspend()
3109 mutex_lock(&adev->pm.mutex); in kv_dpm_suspend()
3111 kv_dpm_disable(adev); in kv_dpm_suspend()
3113 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; in kv_dpm_suspend()
3114 mutex_unlock(&adev->pm.mutex); in kv_dpm_suspend()
3122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_resume() local
3124 if (adev->pm.dpm_enabled) { in kv_dpm_resume()
3126 mutex_lock(&adev->pm.mutex); in kv_dpm_resume()
3127 kv_dpm_setup_asic(adev); in kv_dpm_resume()
3128 ret = kv_dpm_enable(adev); in kv_dpm_resume()
3130 adev->pm.dpm_enabled = false; in kv_dpm_resume()
3132 adev->pm.dpm_enabled = true; in kv_dpm_resume()
3133 mutex_unlock(&adev->pm.mutex); in kv_dpm_resume()
3134 if (adev->pm.dpm_enabled) in kv_dpm_resume()
3135 amdgpu_pm_compute_clocks(adev); in kv_dpm_resume()
3152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in kv_dpm_print_status() local
3154 dev_info(adev->dev, "KV/KB DPM registers\n"); in kv_dpm_print_status()
3155 dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n", in kv_dpm_print_status()
3157 dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n", in kv_dpm_print_status()
3159 dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n", in kv_dpm_print_status()
3161 dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n", in kv_dpm_print_status()
3163 dev_info(adev->dev, " LCAC_SX0_OVR_SEL=0x%08X\n", in kv_dpm_print_status()
3165 dev_info(adev->dev, " LCAC_SX0_OVR_VAL=0x%08X\n", in kv_dpm_print_status()
3167 dev_info(adev->dev, " LCAC_MC0_OVR_SEL=0x%08X\n", in kv_dpm_print_status()
3169 dev_info(adev->dev, " LCAC_MC0_OVR_VAL=0x%08X\n", in kv_dpm_print_status()
3171 dev_info(adev->dev, " LCAC_MC1_OVR_SEL=0x%08X\n", in kv_dpm_print_status()
3173 dev_info(adev->dev, " LCAC_MC1_OVR_VAL=0x%08X\n", in kv_dpm_print_status()
3175 dev_info(adev->dev, " LCAC_MC2_OVR_SEL=0x%08X\n", in kv_dpm_print_status()
3177 dev_info(adev->dev, " LCAC_MC2_OVR_VAL=0x%08X\n", in kv_dpm_print_status()
3179 dev_info(adev->dev, " LCAC_MC3_OVR_SEL=0x%08X\n", in kv_dpm_print_status()
3181 dev_info(adev->dev, " LCAC_MC3_OVR_VAL=0x%08X\n", in kv_dpm_print_status()
3183 dev_info(adev->dev, " LCAC_CPL_OVR_SEL=0x%08X\n", in kv_dpm_print_status()
3185 dev_info(adev->dev, " LCAC_CPL_OVR_VAL=0x%08X\n", in kv_dpm_print_status()
3187 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n", in kv_dpm_print_status()
3189 dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n", in kv_dpm_print_status()
3191 dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n", in kv_dpm_print_status()
3193 dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n", in kv_dpm_print_status()
3195 dev_info(adev->dev, " SMC_RESP_0=0x%08X\n", in kv_dpm_print_status()
3197 dev_info(adev->dev, " SMC_MSG_ARG_0=0x%08X\n", in kv_dpm_print_status()
3199 dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n", in kv_dpm_print_status()
3201 dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n", in kv_dpm_print_status()
3203 dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n", in kv_dpm_print_status()
3212 static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev, in kv_dpm_set_interrupt_state() argument
3260 static int kv_dpm_process_interrupt(struct amdgpu_device *adev, in kv_dpm_process_interrupt() argument
3272 adev->pm.dpm.thermal.high_to_low = false; in kv_dpm_process_interrupt()
3277 adev->pm.dpm.thermal.high_to_low = true; in kv_dpm_process_interrupt()
3285 schedule_work(&adev->pm.dpm.thermal.work); in kv_dpm_process_interrupt()
3334 static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev) in kv_dpm_set_dpm_funcs() argument
3336 if (adev->pm.funcs == NULL) in kv_dpm_set_dpm_funcs()
3337 adev->pm.funcs = &kv_dpm_funcs; in kv_dpm_set_dpm_funcs()
3345 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev) in kv_dpm_set_irq_funcs() argument
3347 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; in kv_dpm_set_irq_funcs()
3348 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; in kv_dpm_set_irq_funcs()