163 		WREG32(mmBIF_FB_EN, 0);  in gmc_v8_0_mc_stop()
167 		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);  in gmc_v8_0_mc_stop()
181 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v8_0_mc_resume()
185 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v8_0_mc_resume()
271 			WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);  in gmc_v8_0_mc_load_microcode()
275 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_mc_load_microcode()
276 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);  in gmc_v8_0_mc_load_microcode()
280 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_mc_load_microcode()
281 			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));  in gmc_v8_0_mc_load_microcode()
285 			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));  in gmc_v8_0_mc_load_microcode()
288 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);  in gmc_v8_0_mc_load_microcode()
289 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);  in gmc_v8_0_mc_load_microcode()
290 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);  in gmc_v8_0_mc_load_microcode()
307 			WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);  in gmc_v8_0_mc_load_microcode()
343 		WREG32((0xb05 + j), 0x00000000);  in gmc_v8_0_mc_program()
344 		WREG32((0xb06 + j), 0x00000000);  in gmc_v8_0_mc_program()
345 		WREG32((0xb07 + j), 0x00000000);  in gmc_v8_0_mc_program()
346 		WREG32((0xb08 + j), 0x00000000);  in gmc_v8_0_mc_program()
347 		WREG32((0xb09 + j), 0x00000000);  in gmc_v8_0_mc_program()
349 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);  in gmc_v8_0_mc_program()
359 	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,  in gmc_v8_0_mc_program()
361 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,  in gmc_v8_0_mc_program()
363 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,  in gmc_v8_0_mc_program()
367 	WREG32(mmMC_VM_FB_LOCATION, tmp);  in gmc_v8_0_mc_program()
369 	WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));  in gmc_v8_0_mc_program()
370 	WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));  in gmc_v8_0_mc_program()
371 	WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);  in gmc_v8_0_mc_program()
372 	WREG32(mmMC_VM_AGP_BASE, 0);  in gmc_v8_0_mc_program()
373 	WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);  in gmc_v8_0_mc_program()
374 	WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);  in gmc_v8_0_mc_program()
380 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);  in gmc_v8_0_mc_program()
384 	WREG32(mmHDP_MISC_CNTL, tmp);  in gmc_v8_0_mc_program()
387 	WREG32(mmHDP_HOST_PATH_CNTL, tmp);  in gmc_v8_0_mc_program()
483 	WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);  in gmc_v8_0_gart_flush_gpu_tlb()
486 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);  in gmc_v8_0_gart_flush_gpu_tlb()
562 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_set_fault_enable_default()
595 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v8_0_gart_enable()
605 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v8_0_gart_enable()
609 	WREG32(mmVM_L2_CNTL2, tmp);  in gmc_v8_0_gart_enable()
614 	WREG32(mmVM_L2_CNTL3, tmp);  in gmc_v8_0_gart_enable()
629 	WREG32(mmVM_L2_CNTL4, tmp);  in gmc_v8_0_gart_enable()
631 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);  in gmc_v8_0_gart_enable()
632 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);  in gmc_v8_0_gart_enable()
633 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);  in gmc_v8_0_gart_enable()
634 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v8_0_gart_enable()
636 	WREG32(mmVM_CONTEXT0_CNTL2, 0);  in gmc_v8_0_gart_enable()
641 	WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_gart_enable()
643 	WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);  in gmc_v8_0_gart_enable()
644 	WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);  in gmc_v8_0_gart_enable()
645 	WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);  in gmc_v8_0_gart_enable()
652 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);  in gmc_v8_0_gart_enable()
653 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);  in gmc_v8_0_gart_enable()
656 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,  in gmc_v8_0_gart_enable()
659 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,  in gmc_v8_0_gart_enable()
664 	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,  in gmc_v8_0_gart_enable()
666 	WREG32(mmVM_CONTEXT1_CNTL2, 4);  in gmc_v8_0_gart_enable()
679 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_gart_enable()
721 	WREG32(mmVM_CONTEXT0_CNTL, 0);  in gmc_v8_0_gart_disable()
722 	WREG32(mmVM_CONTEXT1_CNTL, 0);  in gmc_v8_0_gart_disable()
728 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v8_0_gart_disable()
732 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v8_0_gart_disable()
733 	WREG32(mmVM_L2_CNTL2, 0);  in gmc_v8_0_gart_disable()
1214 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v8_0_soft_reset()
1220 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v8_0_soft_reset()
1254 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1258 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1264 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()
1268 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v8_0_vm_fault_interrupt_state()