88 	u32 tmp;  in gmc_v7_0_mc_wait_for_idle()  local
92 		tmp = RREG32(mmSRBM_STATUS) & 0x1F00;  in gmc_v7_0_mc_wait_for_idle()
93 		if (!tmp)  in gmc_v7_0_mc_wait_for_idle()
126 	u32 tmp;  in gmc_v7_0_mc_resume()  local
129 	tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);  in gmc_v7_0_mc_resume()
130 	tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);  in gmc_v7_0_mc_resume()
131 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);  in gmc_v7_0_mc_resume()
133 	tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);  in gmc_v7_0_mc_resume()
134 	tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);  in gmc_v7_0_mc_resume()
135 	WREG32(mmBIF_FB_EN, tmp);  in gmc_v7_0_mc_resume()
297 	u32 tmp;  in gmc_v7_0_mc_program()  local
324 	tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;  in gmc_v7_0_mc_program()
325 	tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);  in gmc_v7_0_mc_program()
326 	WREG32(mmMC_VM_FB_LOCATION, tmp);  in gmc_v7_0_mc_program()
341 	tmp = RREG32(mmHDP_MISC_CNTL);  in gmc_v7_0_mc_program()
342 	tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);  in gmc_v7_0_mc_program()
343 	WREG32(mmHDP_MISC_CNTL, tmp);  in gmc_v7_0_mc_program()
345 	tmp = RREG32(mmHDP_HOST_PATH_CNTL);  in gmc_v7_0_mc_program()
346 	WREG32(mmHDP_HOST_PATH_CNTL, tmp);  in gmc_v7_0_mc_program()
360 	u32 tmp;  in gmc_v7_0_mc_init()  local
364 	tmp = RREG32(mmMC_ARB_RAMCFG);  in gmc_v7_0_mc_init()
365 	if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {  in gmc_v7_0_mc_init()
370 	tmp = RREG32(mmMC_SHARED_CHMAP);  in gmc_v7_0_mc_init()
371 	switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {  in gmc_v7_0_mc_init()
484 	u32 tmp;  in gmc_v7_0_set_fault_enable_default()  local
486 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_set_fault_enable_default()
487 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
489 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
491 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
493 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
495 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
497 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,  in gmc_v7_0_set_fault_enable_default()
499 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_set_fault_enable_default()
516 	u32 tmp;  in gmc_v7_0_gart_enable()  local
526 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_enable()
527 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);  in gmc_v7_0_gart_enable()
528 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);  in gmc_v7_0_gart_enable()
529 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);  in gmc_v7_0_gart_enable()
530 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);  in gmc_v7_0_gart_enable()
531 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);  in gmc_v7_0_gart_enable()
532 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v7_0_gart_enable()
534 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_enable()
535 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);  in gmc_v7_0_gart_enable()
536 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);  in gmc_v7_0_gart_enable()
537 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);  in gmc_v7_0_gart_enable()
538 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);  in gmc_v7_0_gart_enable()
539 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);  in gmc_v7_0_gart_enable()
540 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);  in gmc_v7_0_gart_enable()
541 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);  in gmc_v7_0_gart_enable()
542 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v7_0_gart_enable()
543 	tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);  in gmc_v7_0_gart_enable()
544 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);  in gmc_v7_0_gart_enable()
545 	WREG32(mmVM_L2_CNTL2, tmp);  in gmc_v7_0_gart_enable()
546 	tmp = RREG32(mmVM_L2_CNTL3);  in gmc_v7_0_gart_enable()
547 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);  in gmc_v7_0_gart_enable()
548 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4);  in gmc_v7_0_gart_enable()
549 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4);  in gmc_v7_0_gart_enable()
550 	WREG32(mmVM_L2_CNTL3, tmp);  in gmc_v7_0_gart_enable()
558 	tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_gart_enable()
559 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);  in gmc_v7_0_gart_enable()
560 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);  in gmc_v7_0_gart_enable()
561 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);  in gmc_v7_0_gart_enable()
562 	WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_gart_enable()
588 	tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_gart_enable()
589 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);  in gmc_v7_0_gart_enable()
590 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);  in gmc_v7_0_gart_enable()
591 	tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,  in gmc_v7_0_gart_enable()
593 	WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_gart_enable()
600 		tmp = RREG32(mmCHUB_CONTROL);  in gmc_v7_0_gart_enable()
601 		tmp &= ~BYPASS_VM;  in gmc_v7_0_gart_enable()
602 		WREG32(mmCHUB_CONTROL, tmp);  in gmc_v7_0_gart_enable()
638 	u32 tmp;  in gmc_v7_0_gart_disable()  local
644 	tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);  in gmc_v7_0_gart_disable()
645 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);  in gmc_v7_0_gart_disable()
646 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);  in gmc_v7_0_gart_disable()
647 	tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);  in gmc_v7_0_gart_disable()
648 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);  in gmc_v7_0_gart_disable()
650 	tmp = RREG32(mmVM_L2_CNTL);  in gmc_v7_0_gart_disable()
651 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);  in gmc_v7_0_gart_disable()
652 	WREG32(mmVM_L2_CNTL, tmp);  in gmc_v7_0_gart_disable()
697 		u64 tmp = RREG32(mmMC_VM_FB_OFFSET);  in gmc_v7_0_vm_init()  local
698 		tmp <<= 22;  in gmc_v7_0_vm_init()
699 		adev->vm_manager.vram_base_offset = tmp;  in gmc_v7_0_vm_init()
924 		u32 tmp = RREG32(mmMC_SEQ_MISC0);  in gmc_v7_0_sw_init()  local
925 		tmp &= MC_SEQ_MISC0__MT__MASK;  in gmc_v7_0_sw_init()
926 		adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);  in gmc_v7_0_sw_init()
1087 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_is_idle()  local
1089 	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |  in gmc_v7_0_is_idle()
1099 	u32 tmp;  in gmc_v7_0_wait_for_idle()  local
1104 		tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |  in gmc_v7_0_wait_for_idle()
1109 		if (!tmp)  in gmc_v7_0_wait_for_idle()
1230 	u32 tmp = RREG32(mmSRBM_STATUS);  in gmc_v7_0_soft_reset()  local
1232 	if (tmp & SRBM_STATUS__VMC_BUSY_MASK)  in gmc_v7_0_soft_reset()
1236 	if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |  in gmc_v7_0_soft_reset()
1252 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1253 		tmp |= srbm_soft_reset;  in gmc_v7_0_soft_reset()
1254 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);  in gmc_v7_0_soft_reset()
1255 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v7_0_soft_reset()
1256 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1260 		tmp &= ~srbm_soft_reset;  in gmc_v7_0_soft_reset()
1261 		WREG32(mmSRBM_SOFT_RESET, tmp);  in gmc_v7_0_soft_reset()
1262 		tmp = RREG32(mmSRBM_SOFT_RESET);  in gmc_v7_0_soft_reset()
1281 	u32 tmp;  in gmc_v7_0_vm_fault_interrupt_state()  local
1292 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1293 		tmp &= ~bits;  in gmc_v7_0_vm_fault_interrupt_state()
1294 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1296 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1297 		tmp &= ~bits;  in gmc_v7_0_vm_fault_interrupt_state()
1298 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1302 		tmp = RREG32(mmVM_CONTEXT0_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1303 		tmp |= bits;  in gmc_v7_0_vm_fault_interrupt_state()
1304 		WREG32(mmVM_CONTEXT0_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()
1306 		tmp = RREG32(mmVM_CONTEXT1_CNTL);  in gmc_v7_0_vm_fault_interrupt_state()
1307 		tmp |= bits;  in gmc_v7_0_vm_fault_interrupt_state()
1308 		WREG32(mmVM_CONTEXT1_CNTL, tmp);  in gmc_v7_0_vm_fault_interrupt_state()