179 	err = request_firmware(&adev->mc.fw, fw_name, adev->dev);  in gmc_v7_0_init_microcode()
182 	err = amdgpu_ucode_validate(adev->mc.fw);  in gmc_v7_0_init_microcode()
189 		release_firmware(adev->mc.fw);  in gmc_v7_0_init_microcode()
190 		adev->mc.fw = NULL;  in gmc_v7_0_init_microcode()
211 	if (!adev->mc.fw)  in gmc_v7_0_mc_load_microcode()
214 	hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data;  in gmc_v7_0_mc_load_microcode()
217 	adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version);  in gmc_v7_0_mc_load_microcode()
220 		(adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));  in gmc_v7_0_mc_load_microcode()
223 		(adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));  in gmc_v7_0_mc_load_microcode()
273 				       struct amdgpu_mc *mc)  in gmc_v7_0_vram_gtt_location()  argument
275 	if (mc->mc_vram_size > 0xFFC0000000ULL) {  in gmc_v7_0_vram_gtt_location()
278 		mc->real_vram_size = 0xFFC0000000ULL;  in gmc_v7_0_vram_gtt_location()
279 		mc->mc_vram_size = 0xFFC0000000ULL;  in gmc_v7_0_vram_gtt_location()
281 	amdgpu_vram_location(adev, &adev->mc, 0);  in gmc_v7_0_vram_gtt_location()
282 	adev->mc.gtt_base_align = 0;  in gmc_v7_0_vram_gtt_location()
283 	amdgpu_gtt_location(adev, mc);  in gmc_v7_0_vram_gtt_location()
319 	       adev->mc.vram_start >> 12);  in gmc_v7_0_mc_program()
321 	       adev->mc.vram_end >> 12);  in gmc_v7_0_mc_program()
324 	tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16;  in gmc_v7_0_mc_program()
325 	tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF);  in gmc_v7_0_mc_program()
328 	WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8));  in gmc_v7_0_mc_program()
401 	adev->mc.vram_width = numchan * chansize;  in gmc_v7_0_mc_init()
403 	adev->mc.aper_base = pci_resource_start(adev->pdev, 0);  in gmc_v7_0_mc_init()
404 	adev->mc.aper_size = pci_resource_len(adev->pdev, 0);  in gmc_v7_0_mc_init()
406 	adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v7_0_mc_init()
407 	adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;  in gmc_v7_0_mc_init()
408 	adev->mc.visible_vram_size = adev->mc.aper_size;  in gmc_v7_0_mc_init()
414 		adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);  in gmc_v7_0_mc_init()
416 		adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;  in gmc_v7_0_mc_init()
418 	gmc_v7_0_vram_gtt_location(adev, &adev->mc);  in gmc_v7_0_mc_init()
552 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12);  in gmc_v7_0_gart_enable()
553 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12);  in gmc_v7_0_gart_enable()
607 		 (unsigned)(adev->mc.gtt_size >> 20),  in gmc_v7_0_gart_enable()
908 	return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);  in gmc_v7_0_late_init()
922 		adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;  in gmc_v7_0_sw_init()
926 		adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);  in gmc_v7_0_sw_init()
929 	r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);  in gmc_v7_0_sw_init()
933 	r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);  in gmc_v7_0_sw_init()
947 	adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */  in gmc_v7_0_sw_init()
1043 	amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);  in gmc_v7_0_hw_fini()
1407 	adev->mc.vm_fault.num_types = 1;  in gmc_v7_0_set_irq_funcs()
1408 	adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs;  in gmc_v7_0_set_irq_funcs()