3736 	struct vi_mqd *mqd;  in gfx_v8_0_cp_compute_resume()  local
3803 		mqd = (struct vi_mqd *)buf;  in gfx_v8_0_cp_compute_resume()
3804 		mqd->header = 0xC0310800;  in gfx_v8_0_cp_compute_resume()
3805 		mqd->compute_pipelinestat_enable = 0x00000001;  in gfx_v8_0_cp_compute_resume()
3806 		mqd->compute_static_thread_mgmt_se0 = 0xffffffff;  in gfx_v8_0_cp_compute_resume()
3807 		mqd->compute_static_thread_mgmt_se1 = 0xffffffff;  in gfx_v8_0_cp_compute_resume()
3808 		mqd->compute_static_thread_mgmt_se2 = 0xffffffff;  in gfx_v8_0_cp_compute_resume()
3809 		mqd->compute_static_thread_mgmt_se3 = 0xffffffff;  in gfx_v8_0_cp_compute_resume()
3810 		mqd->compute_misc_reserved = 0x00000003;  in gfx_v8_0_cp_compute_resume()
3822 		mqd->cp_hqd_eop_base_addr_lo =  in gfx_v8_0_cp_compute_resume()
3824 		mqd->cp_hqd_eop_base_addr_hi =  in gfx_v8_0_cp_compute_resume()
3835 		mqd->cp_hqd_pq_doorbell_control = tmp;  in gfx_v8_0_cp_compute_resume()
3838 		mqd->cp_hqd_dequeue_request = 0;  in gfx_v8_0_cp_compute_resume()
3839 		mqd->cp_hqd_pq_rptr = 0;  in gfx_v8_0_cp_compute_resume()
3840 		mqd->cp_hqd_pq_wptr= 0;  in gfx_v8_0_cp_compute_resume()
3848 			WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);  in gfx_v8_0_cp_compute_resume()
3849 			WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);  in gfx_v8_0_cp_compute_resume()
3850 			WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);  in gfx_v8_0_cp_compute_resume()
3854 		mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;  in gfx_v8_0_cp_compute_resume()
3855 		mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);  in gfx_v8_0_cp_compute_resume()
3856 		WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);  in gfx_v8_0_cp_compute_resume()
3857 		WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);  in gfx_v8_0_cp_compute_resume()
3863 		mqd->cp_mqd_control = tmp;  in gfx_v8_0_cp_compute_resume()
3867 		mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;  in gfx_v8_0_cp_compute_resume()
3868 		mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);  in gfx_v8_0_cp_compute_resume()
3869 		WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);  in gfx_v8_0_cp_compute_resume()
3870 		WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);  in gfx_v8_0_cp_compute_resume()
3886 		mqd->cp_hqd_pq_control = tmp;  in gfx_v8_0_cp_compute_resume()
3890 		mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;  in gfx_v8_0_cp_compute_resume()
3891 		mqd->cp_hqd_pq_rptr_report_addr_hi =  in gfx_v8_0_cp_compute_resume()
3894 		       mqd->cp_hqd_pq_rptr_report_addr_lo);  in gfx_v8_0_cp_compute_resume()
3896 		       mqd->cp_hqd_pq_rptr_report_addr_hi);  in gfx_v8_0_cp_compute_resume()
3900 		mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;  in gfx_v8_0_cp_compute_resume()
3901 		mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;  in gfx_v8_0_cp_compute_resume()
3902 		WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);  in gfx_v8_0_cp_compute_resume()
3904 		       mqd->cp_hqd_pq_wptr_poll_addr_hi);  in gfx_v8_0_cp_compute_resume()
3922 			mqd->cp_hqd_pq_doorbell_control = tmp;  in gfx_v8_0_cp_compute_resume()
3925 			mqd->cp_hqd_pq_doorbell_control = 0;  in gfx_v8_0_cp_compute_resume()
3928 		       mqd->cp_hqd_pq_doorbell_control);  in gfx_v8_0_cp_compute_resume()
3932 		mqd->cp_hqd_pq_wptr = ring->wptr;  in gfx_v8_0_cp_compute_resume()
3933 		WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);  in gfx_v8_0_cp_compute_resume()
3934 		mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);  in gfx_v8_0_cp_compute_resume()
3937 		mqd->cp_hqd_vmid = 0;  in gfx_v8_0_cp_compute_resume()
3938 		WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);  in gfx_v8_0_cp_compute_resume()
3943 		mqd->cp_hqd_persistent_state = tmp;  in gfx_v8_0_cp_compute_resume()
3946 		mqd->cp_hqd_active = 1;  in gfx_v8_0_cp_compute_resume()
3947 		WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);  in gfx_v8_0_cp_compute_resume()