612 	adev->gfx.scratch.num_reg = 7;  in gfx_v8_0_scratch_init()
613 	adev->gfx.scratch.reg_base = mmSCRATCH_REG0;  in gfx_v8_0_scratch_init()
614 	for (i = 0; i < adev->gfx.scratch.num_reg; i++) {  in gfx_v8_0_scratch_init()
615 		adev->gfx.scratch.free[i] = true;  in gfx_v8_0_scratch_init()
616 		adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;  in gfx_v8_0_scratch_init()
757 	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);  in gfx_v8_0_init_microcode()
760 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);  in gfx_v8_0_init_microcode()
763 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;  in gfx_v8_0_init_microcode()
764 	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);  in gfx_v8_0_init_microcode()
765 	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);  in gfx_v8_0_init_microcode()
768 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);  in gfx_v8_0_init_microcode()
771 	err = amdgpu_ucode_validate(adev->gfx.me_fw);  in gfx_v8_0_init_microcode()
774 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;  in gfx_v8_0_init_microcode()
775 	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);  in gfx_v8_0_init_microcode()
776 	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);  in gfx_v8_0_init_microcode()
779 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);  in gfx_v8_0_init_microcode()
782 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);  in gfx_v8_0_init_microcode()
785 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;  in gfx_v8_0_init_microcode()
786 	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);  in gfx_v8_0_init_microcode()
787 	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);  in gfx_v8_0_init_microcode()
790 	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);  in gfx_v8_0_init_microcode()
793 	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);  in gfx_v8_0_init_microcode()
794 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;  in gfx_v8_0_init_microcode()
795 	adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);  in gfx_v8_0_init_microcode()
796 	adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);  in gfx_v8_0_init_microcode()
799 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);  in gfx_v8_0_init_microcode()
802 	err = amdgpu_ucode_validate(adev->gfx.mec_fw);  in gfx_v8_0_init_microcode()
805 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;  in gfx_v8_0_init_microcode()
806 	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);  in gfx_v8_0_init_microcode()
807 	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);  in gfx_v8_0_init_microcode()
812 		err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);  in gfx_v8_0_init_microcode()
814 			err = amdgpu_ucode_validate(adev->gfx.mec2_fw);  in gfx_v8_0_init_microcode()
818 				adev->gfx.mec2_fw->data;  in gfx_v8_0_init_microcode()
819 			adev->gfx.mec2_fw_version =  in gfx_v8_0_init_microcode()
821 			adev->gfx.mec2_feature_version =  in gfx_v8_0_init_microcode()
825 			adev->gfx.mec2_fw = NULL;  in gfx_v8_0_init_microcode()
832 		info->fw = adev->gfx.pfp_fw;  in gfx_v8_0_init_microcode()
839 		info->fw = adev->gfx.me_fw;  in gfx_v8_0_init_microcode()
846 		info->fw = adev->gfx.ce_fw;  in gfx_v8_0_init_microcode()
853 		info->fw = adev->gfx.rlc_fw;  in gfx_v8_0_init_microcode()
860 		info->fw = adev->gfx.mec_fw;  in gfx_v8_0_init_microcode()
865 		if (adev->gfx.mec2_fw) {  in gfx_v8_0_init_microcode()
868 			info->fw = adev->gfx.mec2_fw;  in gfx_v8_0_init_microcode()
881 		release_firmware(adev->gfx.pfp_fw);  in gfx_v8_0_init_microcode()
882 		adev->gfx.pfp_fw = NULL;  in gfx_v8_0_init_microcode()
883 		release_firmware(adev->gfx.me_fw);  in gfx_v8_0_init_microcode()
884 		adev->gfx.me_fw = NULL;  in gfx_v8_0_init_microcode()
885 		release_firmware(adev->gfx.ce_fw);  in gfx_v8_0_init_microcode()
886 		adev->gfx.ce_fw = NULL;  in gfx_v8_0_init_microcode()
887 		release_firmware(adev->gfx.rlc_fw);  in gfx_v8_0_init_microcode()
888 		adev->gfx.rlc_fw = NULL;  in gfx_v8_0_init_microcode()
889 		release_firmware(adev->gfx.mec_fw);  in gfx_v8_0_init_microcode()
890 		adev->gfx.mec_fw = NULL;  in gfx_v8_0_init_microcode()
891 		release_firmware(adev->gfx.mec2_fw);  in gfx_v8_0_init_microcode()
892 		adev->gfx.mec2_fw = NULL;  in gfx_v8_0_init_microcode()
901 	if (adev->gfx.mec.hpd_eop_obj) {  in gfx_v8_0_mec_fini()
902 		r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);  in gfx_v8_0_mec_fini()
905 		amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);  in gfx_v8_0_mec_fini()
906 		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);  in gfx_v8_0_mec_fini()
908 		amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);  in gfx_v8_0_mec_fini()
909 		adev->gfx.mec.hpd_eop_obj = NULL;  in gfx_v8_0_mec_fini()
924 	adev->gfx.mec.num_mec = 1;  in gfx_v8_0_mec_init()
925 	adev->gfx.mec.num_pipe = 1;  in gfx_v8_0_mec_init()
926 	adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;  in gfx_v8_0_mec_init()
928 	if (adev->gfx.mec.hpd_eop_obj == NULL) {  in gfx_v8_0_mec_init()
930 				     adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,  in gfx_v8_0_mec_init()
933 				     &adev->gfx.mec.hpd_eop_obj);  in gfx_v8_0_mec_init()
940 	r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);  in gfx_v8_0_mec_init()
945 	r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,  in gfx_v8_0_mec_init()
946 			  &adev->gfx.mec.hpd_eop_gpu_addr);  in gfx_v8_0_mec_init()
952 	r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);  in gfx_v8_0_mec_init()
959 	memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);  in gfx_v8_0_mec_init()
961 	amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);  in gfx_v8_0_mec_init()
962 	amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);  in gfx_v8_0_mec_init()
976 		adev->gfx.config.max_shader_engines = 1;  in gfx_v8_0_gpu_early_init()
977 		adev->gfx.config.max_tile_pipes = 2;  in gfx_v8_0_gpu_early_init()
978 		adev->gfx.config.max_cu_per_sh = 6;  in gfx_v8_0_gpu_early_init()
979 		adev->gfx.config.max_sh_per_se = 1;  in gfx_v8_0_gpu_early_init()
980 		adev->gfx.config.max_backends_per_se = 2;  in gfx_v8_0_gpu_early_init()
981 		adev->gfx.config.max_texture_channel_caches = 2;  in gfx_v8_0_gpu_early_init()
982 		adev->gfx.config.max_gprs = 256;  in gfx_v8_0_gpu_early_init()
983 		adev->gfx.config.max_gs_threads = 32;  in gfx_v8_0_gpu_early_init()
984 		adev->gfx.config.max_hw_contexts = 8;  in gfx_v8_0_gpu_early_init()
986 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
987 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
988 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
989 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
993 		adev->gfx.config.max_shader_engines = 4;  in gfx_v8_0_gpu_early_init()
994 		adev->gfx.config.max_tile_pipes = 16;  in gfx_v8_0_gpu_early_init()
995 		adev->gfx.config.max_cu_per_sh = 16;  in gfx_v8_0_gpu_early_init()
996 		adev->gfx.config.max_sh_per_se = 1;  in gfx_v8_0_gpu_early_init()
997 		adev->gfx.config.max_backends_per_se = 4;  in gfx_v8_0_gpu_early_init()
998 		adev->gfx.config.max_texture_channel_caches = 16;  in gfx_v8_0_gpu_early_init()
999 		adev->gfx.config.max_gprs = 256;  in gfx_v8_0_gpu_early_init()
1000 		adev->gfx.config.max_gs_threads = 32;  in gfx_v8_0_gpu_early_init()
1001 		adev->gfx.config.max_hw_contexts = 8;  in gfx_v8_0_gpu_early_init()
1003 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1004 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1005 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1006 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1010 		adev->gfx.config.max_shader_engines = 4;  in gfx_v8_0_gpu_early_init()
1011 		adev->gfx.config.max_tile_pipes = 8;  in gfx_v8_0_gpu_early_init()
1012 		adev->gfx.config.max_cu_per_sh = 8;  in gfx_v8_0_gpu_early_init()
1013 		adev->gfx.config.max_sh_per_se = 1;  in gfx_v8_0_gpu_early_init()
1014 		adev->gfx.config.max_backends_per_se = 2;  in gfx_v8_0_gpu_early_init()
1015 		adev->gfx.config.max_texture_channel_caches = 8;  in gfx_v8_0_gpu_early_init()
1016 		adev->gfx.config.max_gprs = 256;  in gfx_v8_0_gpu_early_init()
1017 		adev->gfx.config.max_gs_threads = 32;  in gfx_v8_0_gpu_early_init()
1018 		adev->gfx.config.max_hw_contexts = 8;  in gfx_v8_0_gpu_early_init()
1020 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1021 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1022 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1023 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1027 		adev->gfx.config.max_shader_engines = 1;  in gfx_v8_0_gpu_early_init()
1028 		adev->gfx.config.max_tile_pipes = 2;  in gfx_v8_0_gpu_early_init()
1029 		adev->gfx.config.max_sh_per_se = 1;  in gfx_v8_0_gpu_early_init()
1030 		adev->gfx.config.max_backends_per_se = 2;  in gfx_v8_0_gpu_early_init()
1040 			adev->gfx.config.max_cu_per_sh = 8;  in gfx_v8_0_gpu_early_init()
1050 			adev->gfx.config.max_cu_per_sh = 6;  in gfx_v8_0_gpu_early_init()
1057 			adev->gfx.config.max_cu_per_sh = 6;  in gfx_v8_0_gpu_early_init()
1066 			adev->gfx.config.max_cu_per_sh = 4;  in gfx_v8_0_gpu_early_init()
1070 		adev->gfx.config.max_texture_channel_caches = 2;  in gfx_v8_0_gpu_early_init()
1071 		adev->gfx.config.max_gprs = 256;  in gfx_v8_0_gpu_early_init()
1072 		adev->gfx.config.max_gs_threads = 32;  in gfx_v8_0_gpu_early_init()
1073 		adev->gfx.config.max_hw_contexts = 8;  in gfx_v8_0_gpu_early_init()
1075 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1076 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1077 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1078 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1082 		adev->gfx.config.max_shader_engines = 1;  in gfx_v8_0_gpu_early_init()
1083 		adev->gfx.config.max_tile_pipes = 2;  in gfx_v8_0_gpu_early_init()
1084 		adev->gfx.config.max_sh_per_se = 1;  in gfx_v8_0_gpu_early_init()
1085 		adev->gfx.config.max_backends_per_se = 1;  in gfx_v8_0_gpu_early_init()
1094 			adev->gfx.config.max_cu_per_sh = 3;  in gfx_v8_0_gpu_early_init()
1100 			adev->gfx.config.max_cu_per_sh = 2;  in gfx_v8_0_gpu_early_init()
1104 		adev->gfx.config.max_texture_channel_caches = 2;  in gfx_v8_0_gpu_early_init()
1105 		adev->gfx.config.max_gprs = 256;  in gfx_v8_0_gpu_early_init()
1106 		adev->gfx.config.max_gs_threads = 16;  in gfx_v8_0_gpu_early_init()
1107 		adev->gfx.config.max_hw_contexts = 8;  in gfx_v8_0_gpu_early_init()
1109 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1110 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1111 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1112 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1116 		adev->gfx.config.max_shader_engines = 2;  in gfx_v8_0_gpu_early_init()
1117 		adev->gfx.config.max_tile_pipes = 4;  in gfx_v8_0_gpu_early_init()
1118 		adev->gfx.config.max_cu_per_sh = 2;  in gfx_v8_0_gpu_early_init()
1119 		adev->gfx.config.max_sh_per_se = 1;  in gfx_v8_0_gpu_early_init()
1120 		adev->gfx.config.max_backends_per_se = 2;  in gfx_v8_0_gpu_early_init()
1121 		adev->gfx.config.max_texture_channel_caches = 4;  in gfx_v8_0_gpu_early_init()
1122 		adev->gfx.config.max_gprs = 256;  in gfx_v8_0_gpu_early_init()
1123 		adev->gfx.config.max_gs_threads = 32;  in gfx_v8_0_gpu_early_init()
1124 		adev->gfx.config.max_hw_contexts = 8;  in gfx_v8_0_gpu_early_init()
1126 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;  in gfx_v8_0_gpu_early_init()
1127 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;  in gfx_v8_0_gpu_early_init()
1128 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;  in gfx_v8_0_gpu_early_init()
1129 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;  in gfx_v8_0_gpu_early_init()
1135 	adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);  in gfx_v8_0_gpu_early_init()
1136 	mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;  in gfx_v8_0_gpu_early_init()
1138 	adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;  in gfx_v8_0_gpu_early_init()
1139 	adev->gfx.config.mem_max_burst_length_bytes = 256;  in gfx_v8_0_gpu_early_init()
1163 			adev->gfx.config.mem_row_size_in_kb = 2;  in gfx_v8_0_gpu_early_init()
1165 			adev->gfx.config.mem_row_size_in_kb = 1;  in gfx_v8_0_gpu_early_init()
1168 		adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;  in gfx_v8_0_gpu_early_init()
1169 		if (adev->gfx.config.mem_row_size_in_kb > 4)  in gfx_v8_0_gpu_early_init()
1170 			adev->gfx.config.mem_row_size_in_kb = 4;  in gfx_v8_0_gpu_early_init()
1173 	adev->gfx.config.shader_engine_tile_size = 32;  in gfx_v8_0_gpu_early_init()
1174 	adev->gfx.config.num_gpus = 1;  in gfx_v8_0_gpu_early_init()
1175 	adev->gfx.config.multi_gpu_tile_size = 64;  in gfx_v8_0_gpu_early_init()
1178 	switch (adev->gfx.config.mem_row_size_in_kb) {  in gfx_v8_0_gpu_early_init()
1190 	adev->gfx.config.gb_addr_config = gb_addr_config;  in gfx_v8_0_gpu_early_init()
1200 	r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);  in gfx_v8_0_sw_init()
1205 	r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);  in gfx_v8_0_sw_init()
1210 	r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);  in gfx_v8_0_sw_init()
1214 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;  in gfx_v8_0_sw_init()
1231 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {  in gfx_v8_0_sw_init()
1232 		ring = &adev->gfx.gfx_ring[i];  in gfx_v8_0_sw_init()
1243 				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,  in gfx_v8_0_sw_init()
1250 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_sw_init()
1258 		ring = &adev->gfx.compute_ring[i];  in gfx_v8_0_sw_init()
1270 				     &adev->gfx.eop_irq, irq_type,  in gfx_v8_0_sw_init()
1298 	adev->gfx.ce_ram_size = 0x8000;  in gfx_v8_0_sw_init()
1314 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v8_0_sw_fini()
1315 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);  in gfx_v8_0_sw_fini()
1316 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v8_0_sw_fini()
1317 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);  in gfx_v8_0_sw_fini()
1330 	switch (adev->gfx.config.mem_row_size_in_kb) {  in gfx_v8_0_tiling_mode_table_init()
1511 			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v8_0_tiling_mode_table_init()
1607 			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v8_0_tiling_mode_table_init()
1801 			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v8_0_tiling_mode_table_init()
1897 			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v8_0_tiling_mode_table_init()
2092 			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v8_0_tiling_mode_table_init()
2188 			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v8_0_tiling_mode_table_init()
2359 			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v8_0_tiling_mode_table_init()
2455 			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v8_0_tiling_mode_table_init()
2627 			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v8_0_tiling_mode_table_init()
2723 			adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;  in gfx_v8_0_tiling_mode_table_init()
2807 	adev->gfx.config.backend_enable_mask = enabled_rbs;  in gfx_v8_0_setup_rb()
2899 	WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2900 	WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2901 	WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2903 	       adev->gfx.config.gb_addr_config & 0x70);  in gfx_v8_0_gpu_init()
2905 	       adev->gfx.config.gb_addr_config & 0x70);  in gfx_v8_0_gpu_init()
2906 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2907 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2908 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);  in gfx_v8_0_gpu_init()
2912 	gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,  in gfx_v8_0_gpu_init()
2913 				 adev->gfx.config.max_sh_per_se,  in gfx_v8_0_gpu_init()
2914 				 adev->gfx.config.max_backends_per_se);  in gfx_v8_0_gpu_init()
2953 		   (adev->gfx.config.sc_prim_fifo_size_frontend <<  in gfx_v8_0_gpu_init()
2955 		   (adev->gfx.config.sc_prim_fifo_size_backend <<  in gfx_v8_0_gpu_init()
2957 		   (adev->gfx.config.sc_hiz_tile_fifo_size <<  in gfx_v8_0_gpu_init()
2959 		   (adev->gfx.config.sc_earlyz_tile_fifo_size <<  in gfx_v8_0_gpu_init()
2971 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v8_0_wait_for_rlc_serdes()
2972 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v8_0_wait_for_rlc_serdes()
3058 	if (!adev->gfx.rlc_fw)  in gfx_v8_0_rlc_load_microcode()
3061 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;  in gfx_v8_0_rlc_load_microcode()
3064 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +  in gfx_v8_0_rlc_load_microcode()
3071 	WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);  in gfx_v8_0_rlc_load_microcode()
3120 		for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v8_0_cp_gfx_enable()
3121 			adev->gfx.gfx_ring[i].ready = false;  in gfx_v8_0_cp_gfx_enable()
3135 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)  in gfx_v8_0_cp_gfx_load_microcode()
3139 		adev->gfx.pfp_fw->data;  in gfx_v8_0_cp_gfx_load_microcode()
3141 		adev->gfx.ce_fw->data;  in gfx_v8_0_cp_gfx_load_microcode()
3143 		adev->gfx.me_fw->data;  in gfx_v8_0_cp_gfx_load_microcode()
3153 		(adev->gfx.pfp_fw->data +  in gfx_v8_0_cp_gfx_load_microcode()
3159 	WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);  in gfx_v8_0_cp_gfx_load_microcode()
3163 		(adev->gfx.ce_fw->data +  in gfx_v8_0_cp_gfx_load_microcode()
3169 	WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);  in gfx_v8_0_cp_gfx_load_microcode()
3173 		(adev->gfx.me_fw->data +  in gfx_v8_0_cp_gfx_load_microcode()
3179 	WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);  in gfx_v8_0_cp_gfx_load_microcode()
3215 	struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];  in gfx_v8_0_cp_gfx_start()
3221 	WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);  in gfx_v8_0_cp_gfx_start()
3311 	ring = &adev->gfx.gfx_ring[0];  in gfx_v8_0_cp_gfx_resume()
3385 		for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v8_0_cp_compute_enable()
3386 			adev->gfx.compute_ring[i].ready = false;  in gfx_v8_0_cp_compute_enable()
3404 	if (!adev->gfx.mec_fw)  in gfx_v8_0_cp_compute_load_microcode()
3409 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;  in gfx_v8_0_cp_compute_load_microcode()
3413 		(adev->gfx.mec_fw->data +  in gfx_v8_0_cp_compute_load_microcode()
3421 	WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);  in gfx_v8_0_cp_compute_load_microcode()
3424 	if (adev->gfx.mec2_fw) {  in gfx_v8_0_cp_compute_load_microcode()
3427 		mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;  in gfx_v8_0_cp_compute_load_microcode()
3431 			(adev->gfx.mec2_fw->data +  in gfx_v8_0_cp_compute_load_microcode()
3438 		WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);  in gfx_v8_0_cp_compute_load_microcode()
3709 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_cp_compute_fini()
3710 		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];  in gfx_v8_0_cp_compute_fini()
3740 	for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {  in gfx_v8_0_cp_compute_resume()
3744 		eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);  in gfx_v8_0_cp_compute_resume()
3766 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_cp_compute_resume()
3767 		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];  in gfx_v8_0_cp_compute_resume()
3966 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_cp_compute_resume()
3967 		struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];  in gfx_v8_0_cp_compute_resume()
4150 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v8_0_print_status()
4392 	mutex_lock(&adev->gfx.gpu_clock_mutex);  in gfx_v8_0_get_gpu_clock_counter()
4396 	mutex_unlock(&adev->gfx.gpu_clock_mutex);  in gfx_v8_0_get_gpu_clock_counter()
4452 	adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;  in gfx_v8_0_early_init()
4453 	adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;  in gfx_v8_0_early_init()
4962 		amdgpu_fence_process(&adev->gfx.gfx_ring[0]);  in gfx_v8_0_eop_irq()
4966 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {  in gfx_v8_0_eop_irq()
4967 			ring = &adev->gfx.compute_ring[i];  in gfx_v8_0_eop_irq()
5050 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)  in gfx_v8_0_set_ring_funcs()
5051 		adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;  in gfx_v8_0_set_ring_funcs()
5053 	for (i = 0; i < adev->gfx.num_compute_rings; i++)  in gfx_v8_0_set_ring_funcs()
5054 		adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;  in gfx_v8_0_set_ring_funcs()
5074 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;  in gfx_v8_0_set_irq_funcs()
5075 	adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;  in gfx_v8_0_set_irq_funcs()
5077 	adev->gfx.priv_reg_irq.num_types = 1;  in gfx_v8_0_set_irq_funcs()
5078 	adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;  in gfx_v8_0_set_irq_funcs()
5080 	adev->gfx.priv_inst_irq.num_types = 1;  in gfx_v8_0_set_irq_funcs()
5081 	adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;  in gfx_v8_0_set_irq_funcs()
5128 	for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {  in gfx_v8_0_get_cu_active_bitmap()
5146 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {  in gfx_v8_0_get_cu_info()
5147 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {  in gfx_v8_0_get_cu_info()
5154 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {  in gfx_v8_0_get_cu_info()